Hi,
I am having trouble building an image with an OOT block for the N310. The
build error is provided below (highlighted in YELLOW). Essentially, the OOT
source code is not found. This happens even on the latest master branch.
However, there is no issue if I target the X310 instead.
I think that there is a bug in the build process. I noticed a recent
commit where there was a line missing from the makefile, but I still get
the error after fixing this. Any suggestions?
Rob
irisheyes5@irisheyes5-hp-z240-sff:~/rfnoc/src/uhd-fpga/usrp3/tools/scripts$
./uhd_image_builder.py blk1 -I $HOME/rfnoc/rfnoc-rob/ -d n310 -t
N310_RFNOC_HG
--Using the following blocks to generate image:
* blk1
Adding CE instantiation file for 'N310_RFNOC_HG'
changing temporarily working directory to
/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/tools/scripts/../../top/n3xx
Setting up a 64-bit FPGA build environment for the USRP-N3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
Environment successfully initialized.
make -f Makefile.n3xx.inc bin NAME=N310_RFNOC_HG ARCH=zynq
PART_ID=xc7z100/ffg900/-2 SFP0_1GBE=1 SFP1_10GBE=1 BUILD_1G=1
BUILD_10G=1 RFNOC=1 N310=1 TOP_MODULE=n3xx EXTRA_DEFS="SFP0_1GBE=1
SFP1_10GBE=1 BUILD_1G=1 BUILD_10G=1 RFNOC=1 N310=1"
make[1]: Entering directory
'/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2017.4 (64-bit)
Using parser configuration from:
/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/dev_config.json
[00:00:00] Executing command: vivado -mode batch -source
/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build_n3xx.tcl -log
build.log -journal n3xx.jou
CRITICAL WARNING: [filemgmt 20-1440] File
'/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v'
already exists in the project as a part of sub-design file
'/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/ddr3_32bit/ddr3_32bit.xci'.
Explicitly adding the file outside the scope of the sub-design can lead to
unintended behaviors and is not recommended.
[00:00:18] Current task: Initialization +++ Current Phase: Starting
[00:00:18] Current task: Initialization +++ Current Phase: Finished
[00:00:18] Executing Tcl: synth_design -top n3xx -part xc7z100ffg900-2
-verilog_define SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define
BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define RFNOC=1
-verilog_define N310=1 -verilog_define GIT_HASH=32'hfebf5eed
[00:00:18] Starting Synthesis Command
CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module
ram_2port
[/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/n310_ps_bd/n310_ps_bd/control/ram_2port.v:12]
CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module
cvita_dest_lookup
[/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/n310_ps_bd/n310_ps_bd/packet_proc/cvita_dest_lookup.v:11]
CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module
cvita_chunker
[/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/n310_ps_bd/n310_ps_bd/packet_proc/cvita_chunker.v:15]
ERROR: [Synth 8-439] module 'noc_block_blk1' not found
[/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v:22]
ERROR: [Synth 8-285] failed synthesizing module 'n3xx_core'
[/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-285] failed synthesizing module 'n3xx'
[/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
[00:05:09] Current task: Synthesis +++ Current Phase: Starting
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
console or run log file for details
[00:05:09] Current task: Synthesis +++ Current Phase: Finished
[00:05:09] Process terminated. Status: Failure
========================================================
Warnings: 321
Critical Warnings: 4
Errors: 4
Makefile.n3xx.inc:118: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory
'/home/irisheyes5/rfnoc/src/uhd-fpga/usrp3/top/n3xx'
Makefile:125: recipe for target 'N310_RFNOC_HG' failed
make: *** [N310_RFNOC_HG] Error 2
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