400 Msps would be 1.6 GB/s for sc16 samples. I think X310 bus_clk is 166.66 MHz for a peak throughput of 166.66 MHz * 8 bytes/cycle = 1.333 GB/s, so it would require two separate replay blocks (separate buses, not just separate channels).
I don't know if the memory bandwidth would be adequate since I haven't tried it, but since the replay block is read-only during operation (not simultaneous write then read like the DMA FIFO), it might be possible. Wade On Wed, Dec 5, 2018 at 3:21 PM Brian Padalino via USRP-users < usrp-users@lists.ettus.com> wrote: > On Wed, Dec 5, 2018 at 4:13 PM Max Thomas via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> >> When attempting to stream different waveforms using both channels of the >> replay block simultaneously to two radios on the same USRP (X310) there are >> under-runs. Any ideas why this is happening? The replay block works as >> expected when using either channel 0 or channel 1, but fails when >> attempting to stream channel 0 and channel 1 simultaneously. >> > > I believe the DRAM connected to the FPGA can't handle 400MHz of bandwidth. > > It might be able to work if you decimated to 100MHz streams and > interpolated each radio by 2x. Is that a possibility? > > Brian > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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