On Fri, Apr 26, 2019 at 6:09 AM Chintan Patel via USRP-users < usrp-users@lists.ettus.com> wrote:
> Hi, > > On the B210 devices which use the AD9361, what is the granularity on the > sample rate supported? I know the max sample rate is 61.44MHz, and that the > BBPLL that drives the ADC sample clock allows for a varying rates, but I am > trying to find what are the values that are actually supported. In other > words, if I set rate = 5.2Msps (or any arbitrary number), what determines > whether I will get that exact rate or a different closest-possible rate? > The code for calculating the BBPLL is here: https://github.com/EttusResearch/uhd/blob/7fab6b807ef5b86c97577170b7b5fdc667e3fa20/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp#L1158 Check UG-570 and the BBPLL section for a block diagram, but the code with the modulus and VCO min/max values should give you at least a decent understanding of what you can hit with the device. Brian
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