Hi Robert, Thanks for the feedback!
> Do you plan to provide pre-built FPGA images containing Theseus Cores in the future for certain USRP devices? I guess this would make it even easier for first time users and would well suit the "batteries included" concept. I've been considering this idea for a while now. I really like the concept of having a few prebuilt bitstreams available, especially for usrp users who maybe haven't gotten into rfnoc or FPGA builds. On the other hand, I'd need a license to build images for the relevant targets, and I'm afraid I don't have access to a license I can use in that capacity. Also the permutations of cores and devices gets pretty large to support. So before I chase this idea down any further, I'm curious if there's broader interest in having prebuilt downloadable bitstreams with a wider selection of rfnoc cores... As a quick audience poll: anyone interested? And what devices/configurations would you most like to see? EJ On Thu, May 2, 2019, 10:24 AM Robert via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi! > > I agree with Johannes that Schmidl&Cox OFDM sync would be a nice > extension. > > Do you plan to provide pre-built FPGA images containing Theseus Cores in > the future for certain USRP devices? I guess this would make it even easier > for first time users and would well suit the "batteries included" concept. > > Cheers > Robert > > -----Original Message----- > From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] On Behalf Of > Johannes Demel via USRP-users > Sent: Thursday, May 02, 2019 9:55 AM > To: usrp-users@lists.ettus.com > Subject: Re: [USRP-users] Introducing Theseus Cores: Open source FPGA > cores for DSP and SDR > > Hi EJ, > > this sounds like a very interesting project. Since you asked for ideas, > I guess it would be nice to have a Schmidl&Cox style OFDM > synchronization block. > > Cheers > Johannes > > Am 29.04.19 um 02:00 schrieb EJ Kreinar via USRP-users: > > Hi all, > > > > I'm very happy to announce the (very modest) release of the Theseus > > Cores project: https://gitlab.com/theseus-cores/theseus-cores > > > > Theseus Cores is designed to provide open source FPGA cores for digital > > signal processing and software defined radio, plus the means to *use* > > the FPGA cores in real life.... In practice, that mostly means FPGA code > > propagates up through RFNoC blocks which have both UHD and Gnuradio > > software hooks for users to attach to. In the future it would be great > > to support other FPGA platforms if there's interest too. > > > > So far, Theseus Cores provides the following RFNoC FPGA blocks and > > corresponding software: > > - *Polyphase M/2 Channelizer*: A polyphase channelizer where each > > channel outputs 2x sample rate and is compatible with > > perfect-reconstruction. Thanks to Phil Vallance for re-implementing the > > channelizer described in his GRCon 2017 presentation-- it works! > > - *"1-to-N" DDC Chain*: Parameterized instantiations of "N" independent > > DDCs, where each DDC is connected to the *first* input (a very basic, > > brute force channelizer). Note I've seen several mailing list > > discussions in the past year about 1-to-4 or 1-to-8 DDC channelizers -- > > this block provides the generalized version of that scenario. > > - *DUC + DDC Rational Resampler*: A "hacked" rational resampler, > > consisting of a DUC and a DDC back-to-back. It's not pretty, but it can > > occasionally be helpful. > > > > Furthermore, in an effort to TRY to create an open source FPGA project > > that doesnt catastrophically break on a regular basis, we've set up > > continuous integration tests for both software and FPGA. Dockerfiles are > > provided here (https://gitlab.com/theseus-cores/theseus-docker). Theseus > > > Cores also pushes tagged docker images for various versions of UHD and > > Gnuradio, where the branches for UHD-3.13, UHD-3.14, UHD's master, and > > gnuradio's maint-3.7 are rebuilt weekly. This may be of auxiliary use to > > people building UHD and gnuradio in a CI scenario: > > https://hub.docker.com/u/theseuscores > > <https://github.com/theseus-cores/theseus-cores> > > *What's next??* It's a modest list of features so far, but I'm sure we > > can all sympathize that things move slowly when developing FPGA code. > > Here's a quick rundown of a few ideas on the horizon: > > - Arbitrary resampling > > - Channel downselection for the M/2 channelizer (currently all channels > > must be output... it's far more useful to select a subset of channels to > > return and just grab those) > > - Channel reconsonstruction *after* the M/2 channelizer (maybe) > > - OFDM receiver (maybe) > > > > We need more ideas and contributors! Now that this thing exists, I would > > LOVE to see Theseus Cores fill itself out with some of the more common > > DSP utilities that really should be available as open-source... it would > > be absolutely amazing to provide a library of components and > > applications for FPGA developers in a similar way that gnuradio provides > > for the software community. Please reach out with suggestions for > > relevant FPGA utilities or applications you'd like to see -- or even > > better, if you have ideas or code you're willing to share with the > > project! If you are interested in getting involved in any way, I would > > be happy to hear from you. > > > > Cheers, > > EJ > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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