Sounds good. I'll allow others to comment on the GNURadio side of things. Let me know if you have any specific HW concerns and I can chime in.
-Daniel On Mon, Jul 22, 2019 at 5:17 PM m2wagner via USRP-users < usrp-users@lists.ettus.com> wrote: > > > Hey Daniel, > > Right now I'm setting an externally generated clock to a nearby frequency > and recording the data to file for later processing. I'd like the LOs to be > disciplined to the recovered clock (I have a clock splitter already). I > suppose I'm most curious to see what GNUradio blocks people have had > success with in similar applications > > -Mark > > Sent from my Verizon, Samsung Galaxy smartphone > > -------- Original message -------- > From: Daniel Jepson <daniel.jep...@ettus.com> > Date: 7/22/19 3:00 PM (GMT-08:00) > To: Mark Wagner <m2wag...@eng.ucsd.edu> > Cc: Usrp Users <usrp-users@lists.ettus.com> > Subject: Re: [USRP-users] Digital TV Clock recovery using N310 and > GNUradio > > Hi Mark, > > A few questions: Is your clock recovery algorithm running in the FPGA? Do > you require the sample clock/LOs to be disciplined to this recovered clock? > > While the N310 does not have a dedicated clock output port, if the > recovered clock is internal to the FPGA you can transmit a copy of it out > the front panel GPIO port and (with a bit of creativity) possibly cable it > into another N310. Just watch your voltage level compatibility. > > -Daniel > > On Mon, Jul 22, 2019 at 4:38 PM Mark Wagner via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hey all, >> >> I'd like to recover the clock tone of a digital TV signal on one USRP >> N310 and use it as the clock input to another N310. Does anyone have >> experience doing something like this? I could use some pointers. >> >> -Mark >> >> -- >> Mark Wagner >> University of California San Diego >> Electrical and Computer Engineering >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > > > -- > > Daniel Jepson > > Digital Hardware Engineer > > National Instruments > > > > O: +1.512.683.6163 > > daniel.jep...@ni.com > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > -- Daniel Jepson Digital Hardware Engineer National Instruments O: +1.512.683.6163 daniel.jep...@ni.com
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