Hi,
As part of an effort to improve capability to store incoming receive chain
samples to files on my SSD without errors ('O' or 'D'), I decided to wire
an X310 noc graph to include the DmaFIFO. My thought was that the DmaFIFO
could better tolerate varying rates of sample consumption at the OS.Before trying this by streaming to a file on my SSD, I first ran a test which streamed to a RAM-based file (60 GB ram filesystem). I used an X310/UBX160 with the default FPGA XG image and initiated a 2-channel receive at 50MS/s (using my C++ app & UHD). To my surprise, I am getting frequent "timeouts" on receive, but not always at the same time. In one case, the receive worked successfully for 28 secs (2 ch, 50 MS/s). In other cases, it timed out immediately or after several seconds. Note that I can reliably run this same test without error if I remove the DmaFIFO. The following works fine: RxRadio -> DDC -> host file (in RAM file system) The following times-out at random times: RxRadio -> DDC -> DmaFIFO -> host file (in RAM file system) What could be the cause? Is there any reason the DmaFIFO shouldn't work in the receive chain? Rob
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