On 12/05/2019 03:17 AM, Emanuel via USRP-users wrote:
Hi everybody,
we are using an external 10MHz clock for the B200mini and have some
concerns/questions about the clocking architecture:
1.Do I see it correctly from the schematics, that the external 10MHz
reference is used in a control-loop within the FPGA to actually steer
the 40MHz VCTCXO with the DAC?
2.We used two B200mini with the same external clock and saw some weird
bumps in the Allan deviation plot, indicating partly contributions
from a whatsoever control loop and from the VCTCXO.
3.Why has the B200mini clocking architecture been chosen like that?
a.Is the same architecture used for the B210 as well?
I can't tell *why* the architecture was chosen as it is. But the B210
has a hardware external-reference PLL, so behaves very differently.
4.How is the control loop for the external clock exactly implemented,
and which parameters are used?
a.Are stability characteristics of the used VCTCXO taken into account?
b.Could those parameters bee changed? If so, where and how?
The control loop is implemented in the FPGA code:
...uhd/fpga-src/usrp3/top/b2xxmini/b205_ref_pll.v
Best regards,
Emanuel
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
