Dear all, I have written a simple RX logic in Verilog and now I want to integrate it inside the FPGA. I have the following questions:
1) What is the correct way to connect it after the DDC (so that I will get 1:1 samples with those from GNURadio)? 2) How should I expose it to the UHD driver? I read the radio_legacy.v example about the custom UHD registers but I couldn't get how to specify the register address mapping. Thank you in advance, Varban
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