Hello Brian

Thanks for your response, actually I tried using DDC 1 to n block as given 
here, but giving 1 to 8 channels have a timing issue, while generating the 
build. So I thought it as an alternative plan.

https://gitlab.com/theseus-cores/theseus-cores/-/blob/master/fpga-rfnoc/README.md#dsp-utilsnoc_block_ddc_1_to_n

Regards
Snehasish

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________________________________
From: Brian Padalino <bpadal...@gmail.com>
Sent: Thursday, April 23, 2020 3:38:02 AM
To: Snehasish Kar <snehasish....@live.com>
Cc: usrp-users@lists.ettus.com <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Modifying RFNoC ddc block for 16 parallel instances

On Wed, Apr 22, 2020 at 6:00 PM Snehasish Kar via USRP-users 
<usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hello

I need to have input 16 input and output port from the RFNoC so that I can 
custom sample rate for each channel. Is it possible to modify the RFNoC DDC 
block and split stream block to achieve this.

Probably not successfully.  They are too large by themselves to just 
instantiate 16 of them.  Moreover, having lots of output ports on a block is 
not really well supported from my experience.  Lastly, having 16 blocks just 
isn't going to work.  The crossbar doesn't have enough ports.  You're better 
off making a block with 1 input and 16 outputs, but, as I mentioned before, 
that is still potentially problematic.

Also, the split stream is pretty finicky.  I don't believe it conforms to the 
AXI spec and might cause lockups.

Lastly, you need to make sure you adhere to the ~200MHz/AXI port rule of thumb.

Do you have a block diagram of what you're trying to achieve?

Brian
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