Jim, I couldn't figure it out quickly enough so I just put my ip in-tree (fpga/usrp3/lib/ip/) and updated the corresponding Ettus Makefile.inc Rob
On Thu, Oct 15, 2020 at 1:40 PM Jim Palladino via USRP-users < [email protected]> wrote: > As a quick update, with my attempt "2" described in the original post, I > actually get the same result as I do with method "1" (I fixed a typo), > although I don't get the critical warning. So, the result of trying to > build the FPGA image is still: > > ... > [00:00:12] Starting Synthesis Command > ERROR: [Synth 8-439] module 'DDS_Test_Signal' not found > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/fpga/rfnoc_block_Block/rfnoc_jjj.v:92] > ERROR: [Synth 8-6156] failed synthesizing module 'jjj_const' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/fpga/rfnoc_block_Block/rfnoc_jjj.v:11] > ERROR: [Synth 8-6156] failed synthesizing module 'rfnoc_block_Block' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/fpga/rfnoc_block_Block/rfnoc_block_Block.v:25] > ERROR: [Synth 8-6156] failed synthesizing module 'rfnoc_image_core' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/icores/e320_rfnoc_image_core.v:14] > ERROR: [Synth 8-6156] failed synthesizing module 'e320_core' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/uhd/fpga/usrp3/top/e320/e320_core.v:18] > ERROR: [Synth 8-6156] failed synthesizing module 'e320' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/uhd/fpga/usrp3/top/e320/e320.v:14] > ERROR: [Common 17-69] Command failed: Synthesis failed - please see the > console or run log file for details > [00:04:25] Current task: Synthesis +++ Current Phase: Starting > [00:04:26] Current task: Synthesis +++ Current Phase: Finished > [00:04:26] Process terminated. Status: Failure > > Thanks, > Jim > > > > ------------------------------ > *From:* USRP-users <[email protected]> on behalf of Jim > Palladino via USRP-users <[email protected]> > *Sent:* Thursday, October 15, 2020 1:13 PM > *To:* [email protected] <[email protected]> > *Subject:* [USRP-users] Adding Xilinx IP to custom RFNoC block > > Hello, > > I'm trying to add a Xilinx DDS to a custom RFNoC block (using UHD 4.0 and > associated gr-ettus repo). To do this, I started building the FPGA image > using the GUI option, stopped the build shortly after Vivado opened, and > saved a Vivado Project. Then, in Vivado I configured/added a Xilinx DDS to > my custom RFNoC block hdl and built the project just fine. > > Now, I'm trying to setup my build file structure so I can use the "make" > flow to build the FPGA image. I've tried several things. > > 1) I copied the xci file directly to my rfnoc/fpga/rfnoc_block_Block > folder. Then, I added the following to the Makefile.srcs file in the same > folder: > > RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword > $(MAKEFILE_LIST)))), rfnoc_block_Block.v noc_shell_Block.v rfnoc_jjj.v > DDS_Test_Signal.xci) > > When I try to build the FPGA image, I get the following critical warning: > CRITICAL WARNING: [Vivado 12-1504] The IP is already part of the fileset > 'sources_1'. Requested source > '/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/fpga/rfnoc_block_Block/DDS_Test_Signal.xci' > will not be added. > > followed by these errors: > ERROR: [Synth 8-439] module 'DDS_Test_Signal' not found > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/XXX/fpga/rfnoc_block_Block/rfnoc_jjj.v:92] > ERROR: [Synth 8-6156] failed synthesizing module 'jjj_const' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/fpga/rfnoc_block_Block/rfnoc_jjj.v:11] > ERROR: [Synth 8-6156] failed synthesizing module 'rfnoc_block_Block' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/fpga/rfnoc_block_Block/rfnoc_block_Block.v:25] > ERROR: [Synth 8-6156] failed synthesizing module 'rfnoc_image_core' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/RFNoC_Custom/rfnoc-peanut/rfnoc/icores/e320_rfnoc_image_core.v:14] > ERROR: [Synth 8-6156] failed synthesizing module 'e320_core' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/uhd/fpga/usrp3/top/e320/e320_core.v:18] > ERROR: [Synth 8-6156] failed synthesizing module 'e320' > [/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/uhd/fpga/usrp3/top/e320/e320.v:14] > ERROR: [Common 17-69] Command failed: Synthesis failed - please see the > console or run log file for details > > > 2) Looking at the rfnoc-example included under uhd/host, I see that this > comment is in Ettus's /rfnoc-example/fpga/Makefile.srcs file: > > # If there are additional modules or IP (other than what is in the RFNoC > block > # subdirectories) that needs to get installed in order to synthesize > blocks from > # this module, list them here: > #RFNOC_OOT_SRCS += $(abspath $(addprefix ${RFNOC_EXAMPLE_DIR}, > #my_other_module.v \ > #ip/my_ip_core/my_ip_core.xci \ > #)) > > So, I created an rfnoc/fpga/ip/DDS_Test_Signal folder and copied the xci > file there. Then, I added the following line to my > /rfnoc/fpga/Makefile.srcs: > > RFNOC_OOT_SRCS += $(abspath $(addprefix ${RFNOC_EXAMPLE_DIR}, > ip/DDS_Test_Signal/DDS_Test_Signal.xci)) > > When I do this, I get: > > Environment successfully initialized. > BUILDER: Checking tools... > * GNU bash, version 4.4.20(1)-release (x86_64-pc-linux-gnu) > * Python 2.7.17 > * Vivado v2019.1 (64-bit) > make[5]: *** No rule to make target > '/home/XXX/Projects/SCISRS/usrp/gnuradio/3.8.2.0_uhd4.0.0.0/src/uhd/fpga/usrp3/top/e320/ip/DDS_Test_Signal/DDS_Test_Signal.xci', > needed by 'bin'. Stop. > Makefile:65: recipe for target 'E320_XG' failed > make[4]: *** [E320_XG] Error 2 > Built target Block_x310_rfnoc_image_core > > > So, I'm obviously not adding the IP correctly. Can anyone point me in the > right direction? > > Thanks, > Jim > > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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