Hi, I suggest you take a look at the addsub RFNoC block, which uses a simple HLS module.
https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/rfnoc_block_addsub.v In that block, I think they just pull in the HDL code generated by the HLS tool, but I assume you could also bring it in as an IP block. Regarding your other questions, I suggest you take a look at this video tutorial, which walks talks a lot about how RFNoC blocks work and walks you through creating one: https://www.youtube.com/watch?v=M9ntwQie9vs Thanks, Wade On Thu, Feb 11, 2021 at 8:55 AM Askar, Ramez via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear Sir or Madam, > > > > I am creating a new IP core in Vivado HLS tool. How do I integrate the > tool with RFNoC 4.0 signal path (static routing)? Do I need to export the > HLS-created IP as Vivadio IP before integration? The IP planned to have IQ > samples in and out and some registers to be programmed from C++ > application. > > Which interfaces must the IQ sample stream have? > > and which interfaces the programable registers must have (Axi-lite or > Axi-Stream)? > > How can I integrate the IP core with the NoC shell? > > > > > > Best regards / Mit freundlichen Grüßen > > -- > Askar, Ramez, M.Sc. > Research Associate / Project Manager / Delegate > > Wireless Communications and Networks > Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute, HHI > Einsteinufer 37, 10587 Berlin, Germany > +49 (0)30 31002-628 > ramez.as...@hhi.fraunhofer.de > www.hhi.fraunhofer.de > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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