Dear Jonathon, Thanks for your prompt reply, I checked the specification but before your reply, I was looking into the *rfnoc_create_verilog.py script *and the block *demo* yaml file. I found the key *fpga_iface, *for control and data, has 2 options:
1.ctrlport or axis_ctrl 2. axis_chdr or axis_pyld_ctxt The specification mentioned them too. However, the RFNoC 4 video talks about payload/context interface so could you please advise which should we use to be consistent? Thanks J On Tue, Mar 16, 2021 at 11:13 AM Jonathon Pendlum < [email protected]> wrote: > Hello Julian, > > For a multiple input / output port block, you will need to use > rfnoc_create_verilog with your own block definition yaml file. The RFNoC > specification (https://files.ettus.com/app_notes/RFNoC_Specification.pdf) > has information on the yaml file format in section 4.2.2. You can also look > at the existing blocks in the UHD source tree for inspiration: > https://github.com/EttusResearch/uhd/tree/master/host/include/uhd/rfnoc/blocks. > For example, take a look at addsub.yml for a block with two fixed input / > output ports and fir_filter.yml for a block where the number of ports is > based on a parameter called NUM_PORTS. > > Jonathon > > On Tue, Mar 16, 2021, 10:15 Julian Casallas <[email protected]> > wrote: > >> Hello, >> >> I went through the Getting Started with RFNoC UHD 4 guide and I >> followed the RfNoC 4 WorkShop - GRCon 2020 to design a RFNoC block, this is >> what I did: >> >> 1. Created the gain block and it works fine following the RFNoC 4 video. >> I checked the HDL files, and I could see the interfaces payload and context >> were created between NoC Shell and the User Logic as expected. >> >> 2. Then I went ahead and created my own block, *not* using the >> *rfnocmodtool *but in this case using the *rfnoc_create_verilog.py *tool >> following the UHD 4 guide based on the same gain.yml file for testing >> purposes, however, the verilog files created in this case do not use >> payload/context approach. >> >> I was hoping that following the UHD 4 guide to design new blocks using >> the python script I could get the same verilog files used in the video. >> >> Therefore, my question is, what is the process to add a block with >> multiple inputs and outputs using RFNoC 4? >> >> Thanks >> J >> _______________________________________________ >> USRP-users mailing list -- [email protected] >> To unsubscribe send an email to [email protected] >> >
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