Is it possible that synthesis and generating bitstream in RFNOC blocks make faster??!!! I developed a custom RFNOC block, (I used example gain for RFNOC block) but when I want to synthesize Verilog code It takes long about 2 hours... For building the RFNOC bitstream image I used the below command:
> rfnoc_image_builder -F /home/sp/Documents/uhd-4.1.0.5/fpga -I > /home/sp/Documents/rfnoc-module -p /home/sp/xilinx/Vivado -y > /home/sp/Documents/rfnoc-module/rfnoc/icores/gain_x300_rfnoc_image_core.yml My question is there any option that makes RFNOC synthesis faster? like incremental-implementation-vivado or any same case. https://www.xilinx.com/video/hardware/incremental-implementation-vivado.html Thanks in advance
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