Sadly, I don't think there is one in the UHD repo. I don't know of anyone who has written one.
Wade On Wed, Jun 15, 2022 at 6:19 AM Florent Allard < florent.all...@telecom-paris.fr> wrote: > Hello, > > After having implemented into a RFNoC block the Xilinx IP LDPC Decoder and > Encoder for 5G, I’m trying to implement the Xilinx IP Polar Decoder/Encoder. > > However, the Polar IP requires to be configured with an AXI4-Lite > interface. I know that RFNoC data planes are compliant with AXI-Stream, but > is there an implementation of the AXI4-Lite protocol in the control plane > for example ? > > I found a file doing a mapping of AXI4-Lite to Ctrlport ( > https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/control/axil_ctrlport_master.v), > but what I would need is the other way: receiving a ctrlport command from > RFNoC, and forwarding it as AXI4-Lite to the Xilinx IP block. Does this > exist ? > > Thank you for your help, > > Florent > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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