Hi Stefani,
I don't think even I could find that CPLD design code. Also, I'm honestly having a very
hard time figuring out what you'd achieve by that – the CPLD really does but a tiny bit of
logic/timing glue on the UBX; what is it that you want to achieve by modifying it? Maybe
we can help you finding an alternative implementation e.g. on the FPGA or even less
work-intense in software?
Best regards,
Marcus
On 07.07.22 11:51, STEFANI, Maurizio (External) via USRP-users wrote:
HI,
I need to program the ubx-160 via FPGA using my VHDL code.
Basically the UBX-160 is managed by a PLD but I have not the data format and protocol to
be used.
Is there someone can help me with these info about the format to program the
ubx?
Thank you in advance
Maurizo stefani
The information in this e-mail is confidential. The contents may not be disclosed or
used by anyone other than the addressee. Access to this e-mail by anyone else is
unauthorised.
If you are not the intended recipient, please notify Airbus immediately and delete this
e-mail.
Airbus cannot accept any responsibility for the accuracy or completeness of this e-mail
as it has been sent over public networks. If you have any concerns over the content of
this message or its Accuracy or Integrity, please contact Airbus immediately.
All outgoing e-mails from Airbus are checked using regularly updated virus scanning
software but you should take whatever measures you deem to be appropriate to ensure that
this message and any attachments are virus free.
_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-le...@lists.ettus.com
_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-le...@lists.ettus.com