Hi every one! I´m facing some problems to synthesize a proyect that has a Xilinx IP, a FIFO Generator. I´ve been following this example but it didnt work.
https://github.com/EttusResearch/uhd/tree/master/host/examples/rfnoc-example The synthesis return me this: 'fifo_generator_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. These are the modifications I have made: In rfnoc/fpga, i added the folder ip/fifo_generator_0 with the next Makefile.inc `include $(TOOLS_DIR)/make/viv_ip_builder.mak` `LIB_IP_FIFO_GENERATOR_SRCS = $(addprefix $(IP_BUILD_DIR)/fifo_generator_0/, \` `fifo_generator_0.xci \` `synth/fifo_generator_0.vhd \` `)` `.INTERMEDIATE: LIB_FIFO_GENERATOR_TRGT` `$(LIB_IP_FIFO_GENERATOR_SRCS): LIB_IP_FIFO_GENERATOR_TRGT` ` @:` `LIB_IP_FIFO_GENERATOR_TRGT: $(OOT_FPGA_DIR)/ip/fifo_generator_0/fifo_generator_0.xci` ` $(call BUILD_VIVADO_IP,fifo_generator_0,$(ARCH),$(PART_ID),$(OOT_FPGA_DIR)/ip,$(IP_BUILD_DIR),0`) and in the Makefile.src of rfnoc/fpga i added: `include $(OOT_FPGA_DIR)/ip/fifo_generator_0/Makefile.inc` `LIB_IP_XCI_SRCS += $(LIB_IP_FIFO_GENERATOR_SRCS)` In the Makefile of my rfnoc, i added these lines: `OOT_FPGA_DIR = $(dir $(abspath $(firstword $(MAKEFILE_LIST))))/../` `include $(OOT_FPGA_DIR)/ip/fifo_generator_0/Makefile.inc` Finally, I have made sure that Makefile.e320.inx had LIB_IP_XCI_SRCS. How can i solve it? Kind Regards Adrían
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