Hi Adrián, It is possible to do a post-synthesis simulation, but that's an advanced topic and I wouldn't recommend it unless you suspect you've found a bug in Vivado synthesis. There's no way to do a post-implementation simulation that I know of.
If you want to do a normal simulation and write your own HDL testbench (this standard best practice and is what I recommend), you can take a look at: https://files.ettus.com/manual/md_usrp3_simulation.html There are also lots of examples of simulations in the UHD repo. Search for files named *_tb.sv for examples. Another option for debugging is to use an ILA (Integrated Logic Analyzer). This is usually a last resort, when you have written a testbench but still haven't found any issues. For instructions, see: https://kb.ettus.com/Debugging_FPGA_images Wade On Wed, Oct 26, 2022 at 5:54 AM <adri96r...@gmail.com> wrote: > Hi everyone, > > > I was wondering if it is possible to make a simulation,, and how, after > sythesis or implementation because i am not getting the results that i was > expecting and i don´t know why. > > > Thanks in advance. > > > Adrián Campos > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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