Hi, i am using a XG-100 FPGA and moved from UHD4.0 to UHD4.2 and found out that master clock rate changed from 125 to 122.88MHz. in my application i need radio clock to be 125MHz but it seems it's not possible, at least with the 100 MHz bandwidth variant. is there anything i can do to restore sampling frequency to 125 MHz? thanks,
Dario Pennisi
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