You probably need to install Xilinx patch AR76780. See the dependencies section in the manual for links to the patch:
https://files.ettus.com/manual/md_usrp3_build_instructions.html UHD has already been updated to give you an error when this patch is not installed and you try to build the FPGA, but that wasn't fixed until after 4.3 was released. Wade On Tue, Jan 3, 2023 at 2:40 PM <ri28...@mit.edu> wrote: > Here are my next steps: > > 1. > > git clone https://github.com/EttusResearch/uhd.git clean_uhd > 2. > > git checkout v4.3.0.0 > 3. > > source setupenv.sh --vivado-path=/path/to/Xilinx/Vivado/ > 4. > > make cleanall > 5. > > make X310_XG > > I get a very similar error: > > ======================================================== > > BUILDER: Building IP axi_hb31 > > ======================================================== > > BUILDER: Staging IP in build directory... > > BUILDER: Reserving IP location: > /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31 > > BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2... > > BUILDER: Building IP... > > [00:00:00] Executing command: vivado -mode batch -source > /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl > -log axi_hb31.log -nojournal > > [00:00:13] Current task: Initialization +++ Current Phase: Starting > > WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked: > > CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the > following file is locked: > /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci > > CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the > following file is locked: > /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci > > [00:00:13] Current task: Initialization +++ Current Phase: Finished > > [00:00:13] Executing Tcl: synth_design -top axi_hb31 -part > xc7k410tffg900-2 -mode out_of_context > > [00:00:13] Starting Synthesis Command > > WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products > for Synthesis target. These output products could be required for > synthesis, please generate the output products using the generate_target or > synth_ip command before running synth_design. > > WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked: > > ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources > specified > > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' > > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' > > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' > > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' > > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml' > > ERROR: [Vivado 12-398] No designs are open > > [00:00:14] Current task: Synthesis +++ Current Phase: Starting > > [00:00:14] Current task: Synthesis +++ Current Phase: Finished > > [00:00:14] Process terminated. Status: Failure > > ======================================================== > > Warnings: 3 > > Critical Warnings: 7 > > Errors: 8 > > BUILDER: Releasing IP location: > /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31 > > make[1]: *** > [/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20: > LIB_IP_AXI_HB31_TRGT] Error 1 > > make[1]: Leaving directory > '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300' > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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