I have the vivado project saved now, thanks for your help! For the simulator files, I am a bit lost as to how it should be created?
I am following these instructions to build the simulator files https://files.ettus.com/manual/md_usrp3_sim_writing_sim_makefile.html. I tried running the viv_simulator with the xsim(and without) and I get this. ``` sudo make viv_simulator.mak xsim ``` ``` make: Nothing to be done for 'viv_simulator.mak'. ``` ``` make: *** No rule to make target 'xsim'. Stop. ``` What am I missing here. I also found a folder “/workarea/uhd/fpga/usrp3/top/n3xx/sim” with 6 directories, each with a Makefile and testbench systemverilog file. Is there something I should do with those? Is there a prebuilt simulation I can play around with, or do I need to make one from scratch? Thanks, Joe
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