On Tue, Jan 17, 2023 at 5:53 PM <jmalo...@umass.edu> wrote: > Hello, > > I am currently following the instructions listed at this link: > https://files.ettus.com/manual/md_usrp3_sim_running_testbenches.html > > I am currently having trouble making the testbench for the N321. I have > been able to successfully build the project, however, I am confused in > regards to getting the simulation running on Vivado. > > In which directory should I make the command “make xsim.” I found a folder > “/workarea/uhd/fpga/usrp3/top/n3xx/sim” with 6 directories, each with a > Makefile and testbench systemverilog file. Is there something I should do > with those? When I run “make xsim” in them, I get a “No rule to make > target” error. >
The xsim target is mainly used for simulating specific RFNoC blocks inside of a design - not the full design itself. I don't think there is a full top level design simulation, but I could be wrong. Try navigating to fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc and try running `make xsim` there. What exactly do you want to simulate? Brian
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