Hello, I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this. Here is the output of the vivado -version `Vivado v2021.1_AR76780 (64-bit)` `SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021` `IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021` `Copyright 1986-2021 Xilinx, Inc. All Rights Reserved` And here is the output of the error `========================================================` `BUILDER: Building IP cmplx_mul` `========================================================` `BUILDER: Staging IP in build directory...` `BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul` `BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...` `BUILDER: Building IP...` `[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal` `[00:00:05] Current task: Initialization +++ Current Phase: Starting` `WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:` `CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci` `CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci` `[00:00:05] Current task: Initialization +++ Current Phase: Finished` `[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context` `[00:00:05] Starting Synthesis Command` `WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.` `WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:` `ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified` `ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.` `ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.` `ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.` `ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.` `ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.` `ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.` `CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'` `CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'` `CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'` `CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'` `[00:00:06] Current task: Synthesis +++ Current Phase: Starting` `CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'` `ERROR: [Vivado 12-398] No designs are open` `[00:00:06] Current task: Synthesis +++ Current Phase: Finished` `[00:00:06] Process terminated. Status: Failure` `========================================================` `Warnings: 3` `Critical Warnings: 7` `Errors: 8` `BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul` `make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1` `make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'` `make: *** [Makefile:90: N3X0_IP] Error 2`
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