On Tue, May 30, 2023 at 4:42 PM Mena Ghebranious <m...@chaosinc.com> wrote:
> I don't see any bypass logic in the FPGA code, but in any case, the N320 > only supports three master clock rates, none of which is our desired > sampling rate: > > https://kb.ettus.com/USRP_N300/N310/N320/N321_Getting_Started_Guide#Supported_Sample_Rates > What is your desired sample rate? Bypassing the hbf filtering happens here: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/rfnoc/duc.v#L193 Brian >
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