Hello, The undefined **RFNOC_EDGE_TBL_FILE** macro is a typical error when you try to build a Vivado project generated for X410.
The reason is that the macro is not passed correctly when synthesizing the Vivado project. My workaround was to use synth_design command generated by UHD X410 Makefile. An example: synth_design -top x4xx -part xczu28dr-ffvg1517-2-e -verilog_define QSFP0_0=2 -verilog_define QSFP0_1=2 -verilog_define QSFP0_2=2 -verilog_define QSFP0_3=2 -verilog_define RFBW_200M=1 -verilog_define X410=1 -verilog_define GIT_HASH=32'hfbf186b7 -verilog_define RFNOC_EDGE_TBL_FILE=/home/user/RFSoC/uhd/fpga/usrp3/top/x400/x410_200_static_router.hex -verilog_define RFNOC_IMAGE_CORE_HDR=x410_200_rfnoc_image_core.vh -verilog_define UHD_FPGA_DIR=/home/user/RFSoC/uhd/fpga/usrp3/top/../. I don’t remember exactly how I obtained it. Best Regards,\ Piotr Krysik
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