On 06/10/2023 10:31, Achilleas Anastasopoulos wrote:
Hi there,
we are interested in using the USRPs (X300) to experiment with a
transmission system with feedback and we want to minimize the delay
from the USRP to the air. We want to understand the delays in the
processing.
(We will not be injecting samples through the PC but we are planning
to program directly the USRP FPGA).
My understanding is that there is one source of delay in the
DUC/half-band filtering in the motherboard. How much is this delay?
(delay of halfband filters?)
Another source of delay is inside the ADC chip that also contains
filters.
Is that correct? (I was looking at the Analog Devices chip for the ADC
and I saw halfband filters there as well). How much is this delay?
Finally there is some delay in the analog front end (SBX). Is there an
estimate for this as well?
thanks
Achilleas
The answer can be determined through measurement. It is the case that
some of these delay components will vary depending
on your particular configuration of the DUC, and will sometimes vary
across different FPGA versions, as filter taps and topologies
are "tweaked" to improve performance in some particular dimension.
I don't *think* the ADC chip filters are actually used by the USRP
implementation, but someone correct me if I'm wrong.
The delay through the analog chain will be small, and vary a bit due to
temperature, and component batch variability. For
precise answers, again, laboratory measurement would be necessary.
The analog delay is typically quite small though.
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