I am trying the new UHD 4.6 X440 X4_200 image and I am running into this error after updating the host UHD and flashing the USRP FPGA and FW:
[ERROR] [MPMD::MB_IFACE] Automatic clock detection requested, but no valid clock index given (63). Make sure FPGA bitfile is up to date! [ERROR] [RFNOC::GRAPH] Caught exception while initializing graph: RuntimeError: NotImplementedError: Automatic clock detection requested, but no valid clock index given (63). Make sure FPGA bitfile is up to date! This only happens on the X4_200 image in UHD 4.6, it does not happen with the X4_400 image. My best guess after scanning through the changes is this is the offending commit: https://github.com/EttusResearch/uhd/commit/f215af2ccde6420b685b4ca493c8bd71d28781cb Looks like x440_200_rfnoc_image_core.yml<https://github.com/EttusResearch/uhd/blob/UHD-4.6/fpga/usrp3/top/x400/x440_200_rfnoc_image_core.yml> was not updated with the new “ctrl_clock: _device_.rfnoc_ctrl” and “timebase_clock: _device_.radio” parameters for some reason. This makes the generated Verilog not possess the “.CTRL_CLK_IDX (1)” and “.TB_CLK_IDX (4)” variables. I believe that is what then causes mpmd_mb_iface.cpp<https://github.com/EttusResearch/uhd/blob/c2dd6c1d9989289fc78820d6a70994c3a3a73dc1/host/lib/usrp/mpmd/mpmd_mb_iface.cpp#L178> to error during runtime. Thanks, Zach
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