Forget this email please ... I just need to learn how to use a digital 
oscilloscope.
Aliasing error, all working very well, output clock is at the desired frequency.


----- Mail original -----
De: "friedtj" <[email protected]>
À: "usrp-users" <[email protected]>
Envoyé: Mercredi 8 Janvier 2025 14:19:29
Objet: [USRP-users] Re: X310 clock signal for aliasing (BasicRX daughter board)

Hopefully "last" question: 
I have set 
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, false);
to true and surely enough  I get a continuous clock on the clk_p pin
(J38 pin 2 of https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf) 
which looks like an unbalanced signal since I probe from an oscilloscope
referenced to ground.

However the output signal frequency
1/ appears very unstable (arguably from an oscilloscope trace frequency
measurement), varying by several MHz around a mean value
2/ the mean value is not the one set with "dboard_clock_rate=" even though
this->get_iface()->get_clock_rate(dboard_iface::UNIT_RX);
properly returns the value programmed with this argument. When setting
dboard_clock_rate to 200 MHz, the oscilloscope reads something between
160 and 170 MHz, when setting to 100 MHz the frequency reads 85 to 88 MHz,
and when setting to 50 MHz the reading is 42 - 44 MHz.

I thought maybe the master clock setting would be incorrect but 1/ libuhd
returns 200 MHz master clock and 2/ a value of 184.32 MHz would not match
the observations anyway.

I have read the source code of the other boards enabling set_clock_enabled()
(e.g. db_tvrx.cpp or twinrx_ctrl.cpp) and neither seems to set any other 
parameter
than _db_iface->set_clock_enabled(dboard_iface::UNIT_TX, true);

Am I missing some additional initialization step? PLL locking condition?

Thanks
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