On Tue, Jul 29, 2025 at 11:26 AM Kevin Williams < kevin.willi...@vastech.co.za> wrote:
> This is the issue – my block processes inputs 1:1 without requiring to > give back-pressure. > > > > It decimates, sure, but that is 1:N. > > > > I don’t understand how that radio block can get its fifo nearly full? > I'd recommend approaching this in 2 ways in parallel: - Build an FPGA image with an ILA that has all the ready/valid signals for each stage of your pipeline and trigger when ready is low for multiple clocks or when the overflow occurs and look back at what caused the backup - Simulate the full block design and randomly deassert the CHDR ready signal until you see a similar issue even if you know the cadence can't keep up with your data I really prefer the simulation method over everything since you see all the signals, but sometimes simulations can take forever to run and rebuilding with an ILA can give you a little faster insight. Good luck. Brian
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