A couple of questions: is this for single channel or both channels? what is your sample rate? which version of UHD? Do you happen to know if the replay block is inline with your transmit path (used as a large FIFO buffer)?
Part of the motivation for these questions is that the DRAM on the X310 (1GB total) can be used as a large FIFO (using the replay block). But, the DRAM memory bandwidth cannot support 2 channel operation at 200 MS/s. So, if you are trying to run 2 channels at 200 MS/s, the DRAM cannot be used. Otherwise, it can. Rob On Mon, Aug 4, 2025 at 11:10 AM <[email protected]> wrote: > Hello, > > I am currently working with USRP X310 devices equipped with UBX-160 > daughterboards for both transmission and reception of data streams. To > ensure continuous transmission without encountering memory underflow > issues, I would like to know the maximum buffer memory size that the FPGA > on the X310 can support for handling transmit data. > > Could you please provide guidance or recommendations on this? > > Thank you, > > Getaneh Berie > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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