Hi Jons,\ \ I was assuming you were using sc16 (16bit I and 16 bit Q, therefore 32bits for a single sample) as that is what the large majority of users use.\ \ (See https://files.ettus.com/manual/page_stream.html#stream_datatypes) On the host you can have “larger” data types but the streamers usually translate it to something that the FPGA can understand. I am suspecting that this is the conversion you found in the tx streamer host code.\ \ SC16 is both supported on host and FPGA so that is what almost everyone uses unless you have very specific requirements.
This means samples are 32 bits each on the fpga, and with your CHDR_W of 128, you get 4 samples per clock cycle, therefore you will receive your full 32 samples payload in 8 clock cycles(plus at least one for the prepended header) of the \`chdr_clk\`.\ Of course this is the ideal scenario. In reality, this could of course be more clock cycles depending on the AXI-stream tvalid and tready signals of your block interfaces, of course. Regards,\ Niels
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