Hi Daniel,

is a software solution impossible? You get the RX timestamps, and you could feed the TX burst stream into both the USRP Sink and a block emitting messages describing but the start timestamp TX burst. Messages can feed into a small queue that controls a state machine e.g. in your carrier sense algorithm (and deafens it).

Best,
Marcus

On 9/29/25 12:15 PM, Daniel Estévez wrote:
Hello,

I am implementing a half-duplex modem with GNU Radio and a USRP B2xx that uses CSMA to control medium access. I have a GNU Radio flowgraph with a USRP Source and USRP Sink blocks both set to use the TX/RX antenna. The USRP Sink block uses burst transmission. When a burst is sent, the B2xx automatically switches the receive to the RX2 port.

The issue is that there is enough leakage through the RX2 port that the system is able to receive its own transmit packets with good SNR. This is a problem for the CSMA system because it makes the system detect that the channel is busy while it is transmitting its own packet. Due to the latency between the RX and TX streams in GNU Radio, this prevents the modem from transmitting back-to-back packets (which is allowed and expected by this CSMA scheme), because when the second packet is about to be sent, the modem receiver is still seeing the end of the previous packet and determines that the channel is still busy.

To solve this issue, I would like the USRP Source to receive either zeros, no samples at all, or something that at least does not have so much leakage of its own TX signal.

Is it possible to do this either by appropriate configuration in GNU Radio or 
UHD?

I've been studying the sources of UHD and GNU Radio to see how this could be done. The only thing I have found is that this would be possible with a small change to the FPGA image. For instance, this line

https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/radio_200/radio_legacy.v#L446

could be modified to replace the RX samples by zeros whenever run_rx is 
asserted.

However I would prefer not to build a modified FPGA image for this system, so I was wondering if other solutions exist.

Best,
Daniel.


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