Hi Martin,
I think I’ve done as you asked, but I still don’t see the memory mapped
interface in the HDL. I’ve attached both files for reference.
Because I’m not confident I created the YAML properly, I tried again with the
contents of the replay definition copied into my OOT block. That try gave a
similar result as the first. The associated files are attached and appended
with “v2.”
Could this be a UHD version issue? We’re using 4.8.0.HEAD-0-g308126a4.
Thank you,
Ryan
schema: rfnoc_modtool_args
module_name: halo
version: "1.0"
rfnoc_version: "1.0"
chdr_width: 64
noc_id: 0xF22
# These parameters will be available to the block in the image core.
parameters:
ip_option: HDL_IP
# If there is a separate hdl_parameters section, then this is the list of
# parameters that the HDL module can consume. In this case, we only do some
# sanitization of the ip_option parameter above.
# Note the use of the 'q' (or 'quote') filter. This ensures that the string is
# rendered including quotes, which is necessary for the HDL module to use this
# value as a string parameter.
hdl_parameters:
IP_OPTION: ${ parameters['ip_option'] | q}
checks:
- condition: ${ parameters['ip_option'] in ('HDL_IP', 'IN_TREE_IP',
'OUT_OF_TREE_IP') }
message: "ip_option parameter must be one of HDL_IP, IN_TREE_IP,
OUT_OF_TREE_IP. Is: ${ parameters['ip_option'] }"
clocks:
- name: rfnoc_chdr
freq: "[]"
- name: rfnoc_ctrl
freq: "[]"
- name: ce
freq: "[]"
- name: mem
freq: "[]"
control:
fpga_iface: ctrlport
interface_direction: slave
fifo_depth: 32
clk_domain: rfnoc_chdr
ctrlport:
byte_mode: False
timed: False
has_status: False
data:
fpga_iface: axis_pyld_ctxt
clk_domain: ce
inputs:
in0:
index: 0
item_width: 32
nipc: 1
context_fifo_depth: 2
payload_fifo_depth: 2
format: int32
in1:
index: 1
item_width: 32
nipc: 1
context_fifo_depth: 2
payload_fifo_depth: 2
format: int32
outputs:
out:
index: 0
item_width: 32
nipc: 1
context_fifo_depth: 2
payload_fifo_depth: 2
format: int32
fpga_includes:
# This path is the exact path to the relevant Makefile.srcs in this
repository.
# After installation, the whole directory will become available under a
# similar path, also in the include directories of the image builder, e.g.
# under /usr/share/uhd/rfnoc/fpga/gain/rfnoc_block_gain/Makefile.srcs.
- include: "fpga/custom/rfnoc_block_halo/Makefile.srcs"
# This make variable has to match the one in the file referenced above.
make_var: "$(RFNOC_BLOCK_HALO_SRCS)"
# Because this block requires external IP, we also list that here.
# - include: "fpga/custom/ip/cmplx_mul/Makefile.inc"
# Like above, this is the Make variable that lists the sources for the IP
# we require here.
# make_var: "$(LIB_IP_CMPLX_MUL_SRCS)"
io_ports:
axi_ram:
type: axi4_mm
drive: master
//
// Copyright 2025 <author>
//
// SPDX-License-Identifier: GPL-3.0-or-later
//
// Module: rfnoc_block_halo
//
// Description:
//
// <Add block description here>
//
// Parameters:
//
// THIS_PORTID : Control crossbar port to which this block is connected
// CHDR_W : AXIS-CHDR data bus width
// MTU : Maximum transmission unit (i.e., maximum packet size in
// CHDR words is 2**MTU).
//
`default_nettype none
module rfnoc_block_halo #(
parameter [9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter [5:0] MTU = 10,
parameter ip_option = HDL_IP
)(
// RFNoC Framework Clocks and Resets
input wire rfnoc_chdr_clk,
input wire rfnoc_ctrl_clk,
input wire ce_clk,
input wire mem_clk,
// RFNoC Backend Interface
input wire [511:0] rfnoc_core_config,
output wire [511:0] rfnoc_core_status,
// AXIS-CHDR Input Ports (from framework)
input wire [(2)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
input wire [(2)-1:0] s_rfnoc_chdr_tlast,
input wire [(2)-1:0] s_rfnoc_chdr_tvalid,
output wire [(2)-1:0] s_rfnoc_chdr_tready,
// AXIS-CHDR Output Ports (to framework)
output wire [(1)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
output wire [(1)-1:0] m_rfnoc_chdr_tlast,
output wire [(1)-1:0] m_rfnoc_chdr_tvalid,
input wire [(1)-1:0] m_rfnoc_chdr_tready,
// AXIS-Ctrl Input Port (from framework)
input wire [31:0] s_rfnoc_ctrl_tdata,
input wire s_rfnoc_ctrl_tlast,
input wire s_rfnoc_ctrl_tvalid,
output wire s_rfnoc_ctrl_tready,
// AXIS-Ctrl Output Port (to framework)
output wire [31:0] m_rfnoc_ctrl_tdata,
output wire m_rfnoc_ctrl_tlast,
output wire m_rfnoc_ctrl_tvalid,
input wire m_rfnoc_ctrl_tready
);
//---------------------------------------------------------------------------
// Signal Declarations
//---------------------------------------------------------------------------
// Clocks and Resets
wire ctrlport_clk;
wire ctrlport_rst;
wire axis_data_clk;
wire axis_data_rst;
// CtrlPort Master
wire m_ctrlport_req_wr;
wire m_ctrlport_req_rd;
wire [19:0] m_ctrlport_req_addr;
wire [31:0] m_ctrlport_req_data;
wire m_ctrlport_resp_ack;
wire [31:0] m_ctrlport_resp_data;
// Payload Stream to User Logic: in0
wire [32*1-1:0] m_in0_payload_tdata;
wire [1-1:0] m_in0_payload_tkeep;
wire m_in0_payload_tlast;
wire m_in0_payload_tvalid;
wire m_in0_payload_tready;
// Context Stream to User Logic: in0
wire [CHDR_W-1:0] m_in0_context_tdata;
wire [3:0] m_in0_context_tuser;
wire m_in0_context_tlast;
wire m_in0_context_tvalid;
wire m_in0_context_tready;
// Payload Stream to User Logic: in1
wire [32*1-1:0] m_in1_payload_tdata;
wire [1-1:0] m_in1_payload_tkeep;
wire m_in1_payload_tlast;
wire m_in1_payload_tvalid;
wire m_in1_payload_tready;
// Context Stream to User Logic: in1
wire [CHDR_W-1:0] m_in1_context_tdata;
wire [3:0] m_in1_context_tuser;
wire m_in1_context_tlast;
wire m_in1_context_tvalid;
wire m_in1_context_tready;
// Payload Stream from User Logic: out
wire [32*1-1:0] s_out_payload_tdata;
wire [0:0] s_out_payload_tkeep;
wire s_out_payload_tlast;
wire s_out_payload_tvalid;
wire s_out_payload_tready;
// Context Stream from User Logic: out
wire [CHDR_W-1:0] s_out_context_tdata;
wire [3:0] s_out_context_tuser;
wire s_out_context_tlast;
wire s_out_context_tvalid;
wire s_out_context_tready;
//---------------------------------------------------------------------------
// NoC Shell
//---------------------------------------------------------------------------
noc_shell_halo #(
.CHDR_W (CHDR_W),
.THIS_PORTID (THIS_PORTID),
.MTU (MTU),
.ip_option (ip_option)
) noc_shell_halo_i (
//---------------------
// Framework Interface
//---------------------
// Clock Inputs
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.ce_clk (ce_clk),
.mem_clk (mem_clk),
// Reset Outputs
.rfnoc_chdr_rst (),
.rfnoc_ctrl_rst (),
.ce_rst (),
.mem_rst (),
// CHDR Input Ports (from framework)
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
// CHDR Output Ports (to framework)
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
// AXIS-Ctrl Input Port (from framework)
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
// AXIS-Ctrl Output Port (to framework)
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
//---------------------
// Client Interface
//---------------------
// CtrlPort Clock and Reset
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
// CtrlPort Master
.m_ctrlport_req_wr (m_ctrlport_req_wr),
.m_ctrlport_req_rd (m_ctrlport_req_rd),
.m_ctrlport_req_addr (m_ctrlport_req_addr),
.m_ctrlport_req_data (m_ctrlport_req_data),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
.m_ctrlport_resp_data (m_ctrlport_resp_data),
// AXI-Stream Payload Context Clock and Reset
.axis_data_clk (axis_data_clk),
.axis_data_rst (axis_data_rst),
// Payload Stream to User Logic: in0
.m_in0_payload_tdata (m_in0_payload_tdata),
.m_in0_payload_tkeep (m_in0_payload_tkeep),
.m_in0_payload_tlast (m_in0_payload_tlast),
.m_in0_payload_tvalid (m_in0_payload_tvalid),
.m_in0_payload_tready (m_in0_payload_tready),
// Context Stream to User Logic: in0
.m_in0_context_tdata (m_in0_context_tdata),
.m_in0_context_tuser (m_in0_context_tuser),
.m_in0_context_tlast (m_in0_context_tlast),
.m_in0_context_tvalid (m_in0_context_tvalid),
.m_in0_context_tready (m_in0_context_tready),
// Payload Stream to User Logic: in1
.m_in1_payload_tdata (m_in1_payload_tdata),
.m_in1_payload_tkeep (m_in1_payload_tkeep),
.m_in1_payload_tlast (m_in1_payload_tlast),
.m_in1_payload_tvalid (m_in1_payload_tvalid),
.m_in1_payload_tready (m_in1_payload_tready),
// Context Stream to User Logic: in1
.m_in1_context_tdata (m_in1_context_tdata),
.m_in1_context_tuser (m_in1_context_tuser),
.m_in1_context_tlast (m_in1_context_tlast),
.m_in1_context_tvalid (m_in1_context_tvalid),
.m_in1_context_tready (m_in1_context_tready),
// Payload Stream from User Logic: out
.s_out_payload_tdata (s_out_payload_tdata),
.s_out_payload_tkeep (s_out_payload_tkeep),
.s_out_payload_tlast (s_out_payload_tlast),
.s_out_payload_tvalid (s_out_payload_tvalid),
.s_out_payload_tready (s_out_payload_tready),
// Context Stream from User Logic: out
.s_out_context_tdata (s_out_context_tdata),
.s_out_context_tuser (s_out_context_tuser),
.s_out_context_tlast (s_out_context_tlast),
.s_out_context_tvalid (s_out_context_tvalid),
.s_out_context_tready (s_out_context_tready),
//---------------------------
// RFNoC Backend Interface
//---------------------------
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status)
);
//---------------------------------------------------------------------------
// User Logic
//---------------------------------------------------------------------------
// < Replace this section with your logic >
// Nothing to do yet, so just drive control signals to default values
assign m_ctrlport_resp_ack = 1'b0;
assign m_in0_payload_tready = 1'b0;
assign m_in0_context_tready = 1'b0;
assign m_in1_payload_tready = 1'b0;
assign m_in1_context_tready = 1'b0;
assign s_out_payload_tvalid = 1'b0;
assign s_out_context_tvalid = 1'b0;
endmodule // rfnoc_block_halo
`default_nettype wire
schema: rfnoc_modtool_args
module_name: halo
version: "1.0"
rfnoc_version: "1.0"
chdr_width: 64
noc_id: 0xF22
# These parameters will be available to the block in the image core.
parameters:
ip_option: HDL_IP
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
# If there is a separate hdl_parameters section, then this is the list of
# parameters that the HDL module can consume. In this case, we only do some
# sanitization of the ip_option parameter above.
# Note the use of the 'q' (or 'quote') filter. This ensures that the string is
# rendered including quotes, which is necessary for the HDL module to use this
# value as a string parameter.
hdl_parameters:
IP_OPTION: ${ parameters['ip_option'] | q}
checks:
- condition: ${ parameters['ip_option'] in ('HDL_IP', 'IN_TREE_IP',
'OUT_OF_TREE_IP') }
message: "ip_option parameter must be one of HDL_IP, IN_TREE_IP,
OUT_OF_TREE_IP. Is: ${ parameters['ip_option'] }"
clocks:
- name: rfnoc_chdr
freq: "[]"
- name: rfnoc_ctrl
freq: "[]"
- name: ce
freq: "[]"
- name: mem
freq: "[]"
control:
fpga_iface: ctrlport
interface_direction: slave
fifo_depth: 32
clk_domain: mem
ctrlport:
byte_mode: False
timed: False
has_status: False
data:
fpga_iface: axis_data
clk_domain: mem
inputs:
in:
num_ports: NUM_PORTS
item_width: 32
nipc: MEM_DATA_W/32
info_fifo_depth: 32
payload_fifo_depth: 32
format: int32
mdata_sig: ~
outputs:
out:
num_ports: NUM_PORTS
item_width: 32
nipc: MEM_DATA_W/32
info_fifo_depth: 32
payload_fifo_depth: 2**MTU
sideband_at_end: True
format: int32
mdata_sig: ~
fpga_includes:
# This path is the exact path to the relevant Makefile.srcs in this
repository.
# After installation, the whole directory will become available under a
# similar path, also in the include directories of the image builder, e.g.
# under /usr/share/uhd/rfnoc/fpga/gain/rfnoc_block_gain/Makefile.srcs.
- include: "fpga/custom/rfnoc_block_halo/Makefile.srcs"
# This make variable has to match the one in the file referenced above.
make_var: "$(RFNOC_BLOCK_HALO_SRCS)"
# Because this block requires external IP, we also list that here.
# - include: "fpga/custom/ip/cmplx_mul/Makefile.inc"
# Like above, this is the Make variable that lists the sources for the IP
# we require here.
# make_var: "$(LIB_IP_CMPLX_MUL_SRCS)"
io_ports:
axi_ram:
type: axi4_mm
drive: master
//
// Copyright 2025 <author>
//
// SPDX-License-Identifier: GPL-3.0-or-later
//
// Module: rfnoc_block_halo
//
// Description:
//
// <Add block description here>
//
// Parameters:
//
// THIS_PORTID : Control crossbar port to which this block is connected
// CHDR_W : AXIS-CHDR data bus width
// MTU : Maximum transmission unit (i.e., maximum packet size in
// CHDR words is 2**MTU).
//
`default_nettype none
module rfnoc_block_halo #(
parameter [9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter [5:0] MTU = 10,
parameter ip_option = HDL_IP,
parameter NUM_PORTS = 2,
parameter MEM_DATA_W = 64,
parameter MEM_ADDR_W = 30
)(
// RFNoC Framework Clocks and Resets
input wire rfnoc_chdr_clk,
input wire rfnoc_ctrl_clk,
input wire ce_clk,
input wire mem_clk,
// RFNoC Backend Interface
input wire [511:0] rfnoc_core_config,
output wire [511:0] rfnoc_core_status,
// AXIS-CHDR Input Ports (from framework)
input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
// AXIS-CHDR Output Ports (to framework)
output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
// AXIS-Ctrl Input Port (from framework)
input wire [31:0] s_rfnoc_ctrl_tdata,
input wire s_rfnoc_ctrl_tlast,
input wire s_rfnoc_ctrl_tvalid,
output wire s_rfnoc_ctrl_tready,
// AXIS-Ctrl Output Port (to framework)
output wire [31:0] m_rfnoc_ctrl_tdata,
output wire m_rfnoc_ctrl_tlast,
output wire m_rfnoc_ctrl_tvalid,
input wire m_rfnoc_ctrl_tready
);
//---------------------------------------------------------------------------
// Signal Declarations
//---------------------------------------------------------------------------
// Clocks and Resets
wire ctrlport_clk;
wire ctrlport_rst;
wire axis_data_clk;
wire axis_data_rst;
// CtrlPort Master
wire m_ctrlport_req_wr;
wire m_ctrlport_req_rd;
wire [19:0] m_ctrlport_req_addr;
wire [31:0] m_ctrlport_req_data;
wire m_ctrlport_resp_ack;
wire [31:0] m_ctrlport_resp_data;
// Data Stream to User Logic: in
wire [NUM_PORTS*32*MEM_DATA_W/32-1:0] m_in_axis_tdata;
wire [NUM_PORTS*MEM_DATA_W/32-1:0] m_in_axis_tkeep;
wire [NUM_PORTS-1:0] m_in_axis_tlast;
wire [NUM_PORTS-1:0] m_in_axis_tvalid;
wire [NUM_PORTS-1:0] m_in_axis_tready;
wire [NUM_PORTS*64-1:0] m_in_axis_ttimestamp;
wire [NUM_PORTS-1:0] m_in_axis_thas_time;
wire [NUM_PORTS*16-1:0] m_in_axis_tlength;
wire [NUM_PORTS-1:0] m_in_axis_teov;
wire [NUM_PORTS-1:0] m_in_axis_teob;
// Data Stream from User Logic: out
wire [NUM_PORTS*32*MEM_DATA_W/32-1:0] s_out_axis_tdata;
wire [NUM_PORTS*MEM_DATA_W/32-1:0] s_out_axis_tkeep;
wire [NUM_PORTS-1:0] s_out_axis_tlast;
wire [NUM_PORTS-1:0] s_out_axis_tvalid;
wire [NUM_PORTS-1:0] s_out_axis_tready;
wire [NUM_PORTS*64-1:0] s_out_axis_ttimestamp;
wire [NUM_PORTS-1:0] s_out_axis_thas_time;
wire [NUM_PORTS*16-1:0] s_out_axis_tlength;
wire [NUM_PORTS-1:0] s_out_axis_teov;
wire [NUM_PORTS-1:0] s_out_axis_teob;
//---------------------------------------------------------------------------
// NoC Shell
//---------------------------------------------------------------------------
noc_shell_halo #(
.CHDR_W (CHDR_W),
.THIS_PORTID (THIS_PORTID),
.MTU (MTU),
.ip_option (ip_option),
.NUM_PORTS (NUM_PORTS),
.MEM_DATA_W (MEM_DATA_W),
.MEM_ADDR_W (MEM_ADDR_W)
) noc_shell_halo_i (
//---------------------
// Framework Interface
//---------------------
// Clock Inputs
.rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.ce_clk (ce_clk),
.mem_clk (mem_clk),
// Reset Outputs
.rfnoc_chdr_rst (),
.rfnoc_ctrl_rst (),
.ce_rst (),
.mem_rst (),
// CHDR Input Ports (from framework)
.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
// CHDR Output Ports (to framework)
.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
// AXIS-Ctrl Input Port (from framework)
.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
// AXIS-Ctrl Output Port (to framework)
.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
//---------------------
// Client Interface
//---------------------
// CtrlPort Clock and Reset
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
// CtrlPort Master
.m_ctrlport_req_wr (m_ctrlport_req_wr),
.m_ctrlport_req_rd (m_ctrlport_req_rd),
.m_ctrlport_req_addr (m_ctrlport_req_addr),
.m_ctrlport_req_data (m_ctrlport_req_data),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
.m_ctrlport_resp_data (m_ctrlport_resp_data),
// AXI-Stream Clock and Reset
.axis_data_clk (axis_data_clk),
.axis_data_rst (axis_data_rst),
// Data Stream to User Logic: in
.m_in_axis_tdata (m_in_axis_tdata),
.m_in_axis_tkeep (m_in_axis_tkeep),
.m_in_axis_tlast (m_in_axis_tlast),
.m_in_axis_tvalid (m_in_axis_tvalid),
.m_in_axis_tready (m_in_axis_tready),
.m_in_axis_ttimestamp (m_in_axis_ttimestamp),
.m_in_axis_thas_time (m_in_axis_thas_time),
.m_in_axis_tlength (m_in_axis_tlength),
.m_in_axis_teov (m_in_axis_teov),
.m_in_axis_teob (m_in_axis_teob),
// Data Stream from User Logic: out
.s_out_axis_tdata (s_out_axis_tdata),
.s_out_axis_tkeep (s_out_axis_tkeep),
.s_out_axis_tlast (s_out_axis_tlast),
.s_out_axis_tvalid (s_out_axis_tvalid),
.s_out_axis_tready (s_out_axis_tready),
.s_out_axis_ttimestamp (s_out_axis_ttimestamp),
.s_out_axis_thas_time (s_out_axis_thas_time),
.s_out_axis_tlength (s_out_axis_tlength),
.s_out_axis_teov (s_out_axis_teov),
.s_out_axis_teob (s_out_axis_teob),
//---------------------------
// RFNoC Backend Interface
//---------------------------
.rfnoc_core_config (rfnoc_core_config),
.rfnoc_core_status (rfnoc_core_status)
);
//---------------------------------------------------------------------------
// User Logic
//---------------------------------------------------------------------------
// < Replace this section with your logic >
// Nothing to do yet, so just drive control signals to default values
assign m_ctrlport_resp_ack = 1'b0;
assign m_in_axis_tready = {NUM_PORTS{1'b0}};
assign s_out_axis_tvalid = {NUM_PORTS{1'b0}};
endmodule // rfnoc_block_halo
`default_nettype wire
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