On Wed, Oct 8, 2025 at 2:40 PM <[email protected]> wrote: > Greetings, > > I'm writing to request a heading-check on the design of an RFNoC block > that needs to conditionally save/recall an arbitrary number of samples. I > successfully built & ran a version of the gain example to convince myself > that the build environment was setup correctly. Now I'm struggling to add > the DDR interface to the design. > > My first thought was to port the functionality of the replay block to an > OOT block that contains decision logic to save/recall the samples. By using > the replay block's YAML file as a starting point, I expected rfnoc_modtool > to generate HDL similar to what can be seen in rfnoc_block_replay.v. > Unfortunately, the AXI memory mapped interface is absent in the resulting > HDL. That makes me think that my YAML definition lacks specificity, or that > the interface was added manually. I understand rfnoc_modtool is meant to be > a starting point, so am I expecting too much? > I believe I ran into a similar issue when I was asking about it here:
https://lists.ettus.com/empathy/thread/6UOYGNTMTCP2SFP4PKYH2RF3IWPXWQVJ?hash=6UOYGNTMTCP2SFP4PKYH2RF3IWPXWQVJ#6UOYGNTMTCP2SFP4PKYH2RF3IWPXWQVJ I solved it by hand writing my HDL since I am more proficient in that, but the links to the files in the above post are the places to modify the code generation to get the HDL to better reflect the interfaces you're requesting. HDL is not in my wheelhouse, but I'm working with another engineer who has > experience. We appreciate any insight & advice that this forum provides. > Good luck - hopefully a pull request can come from this work since it's a useful interface for blocks. Brian
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