[email protected] wrote: > https://github.com/EttusResearch/uhd/blob/07a7a92ad6e09cc7e84aae5990aff563a4546e83/fpga/usrp3/top/x400/build_x4xx.tcl#L11tovivado_utils::initialize_project > 1Then in uhd/pga/usrp3/top/x400/ do:source setupenv.shmakeAfter this ends > you should have an \*.xpr file in one of build directories. You can open this > file Vivado. Then find x4xx_ps_rfdc_bd block diagram, open it and edit ZYNQ > configuration to enable the bus that you need. After that I don’t remember if > you have to do synthesis or you can straight away go to File->Export->Export > Hardware and create a zip file with psu_init_gpl.c and a header > (psu_init_gpl.h ?).
Something was messed with this paragraph. It was: https://github.com/EttusResearch/uhd/blob/07a7a92ad6e09cc7e84aae5990aff563a4546e83/fpga/usrp3/top/x400/build_x4xx.tcl#L11 to vivado_utils::initialize_project 1 Then in uhd/pga/usrp3/top/x400/ do: source setupenv.sh\ make After this ends you should have an \*.xpr file in one of build directories. You can open this file Vivado. Then find x4xx_ps_rfdc_bd block diagram, open it and edit ZYNQ configuration to enable the bus that you need. After that I don’t remember if you have to do synthesis or you can straight away go to File->Export->Export Hardware and create a zip file with psu_init_gpl.c and a header (psu_init_gpl.h ?). … Piotr Krysik
_______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
