Hi Luca, did you remove other DSP blocks from the image before adding your block? The resamplers are the most resource-intensive blocks outside of the RF frontend (which unfortunately, can't be removed from the design (at least, easily).
You probably need to keep at least one DDC to provide input data for your block. However, if your block is running at 100MHz, then there's surely ways to optimize DSP usage, like doubling the clock rate and using fewer DSPs that way. --M On Wed, Oct 15, 2025 at 3:13 AM Luca Chen <[email protected]> wrote: > Hi all, > > I am currently working on building a *5G PSS Detector RFNoC Block* on the > *X410* platform. > While using the *RFNoC Image Builder tool* to integrate the RFNoC block, > I encountered the following error: > > *[ERROR: [DRC UTLZ-1] Resource utilization: DSPs over-utilized in Top > Level Design* > This design requires more DSP cells than are available in the target > device. > This design requires 6179 DSP cells, but only 4272 compatible sites are > available in the target device. > Please analyze your synthesis results and constraints to ensure the design > is mapped to Xilinx primitives as expected. > If so, please consider targeting a larger device.] > > In this design, the *custom Vivado IP Core* used in the PSS detector > performs extensive *correlation computations (FIR-based)*, which results > in high DSP utilization. > As a consequence, there are insufficient DSP resources available for > integrating the RFNoC block. > I would like to seek suggestions or best practices on *DSP resource > optimization* for this kind of design. > > *System and Design Details:* > > · *FPGA:* xzcu28dr ffvg1517 1-e > > · *Vivado Version:* 2021.1_AR76780 > > · *Resource Utilization (partial report):* > – Top-level DSP usage: 6179 (available: 4272) > – FIND_PSS_ID (5G PSS Detector RFNoC Block): ~3120 DSPs > – Other modules (excluding FIND_PSS_ID): ~3059 DSPs > > · *Parallelism / Clock:* > – Processing path: 1 channel > – Operating clock: 100 MHz > > Any recommendations on reducing DSP usage, optimizing FIR implementations, > or other design trade-offs to fit within the device constraints would be > greatly appreciated. > > Best regards, > *Luca* > > > > > > *陳冠溢 Luca Chen**❘**SMART LINK BUSINESS.* > > *A :* *耀登集團*❘*桃園市八德區和平路772巷19號* > > *E :* *[email protected]* <http://[email protected]>❘*W :* > *www.auden.com.tw* <http://www.auden.com.tw/> > > > 本資訊及附件可能涉及保密性, > 財產權及特許專權的內容，或已受智慧財產法律保護的專利及商業機密，僅供指定之收件人使用。若您並非被指定之收信人，請告知原發信人；以及請您刪除此信和已列印的文件；亦請勿揭曉本信件內容於任何人。謝謝您的合作。 > > This information and any attachments may contain information that is > confidential, proprietary, privileged or otherwise subject to protection of > intellectual property laws for patents, commercial secrets and is for the > use of the intended recipient only. If you are not the intended recipient, > please notify the sender; delete the information and destroy the hard copy; > and do not disclose the contents to anyone. Thank you for your cooperation. > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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