Dear RFNoC community, during the integration of my custom OOT module on UHD 4.9 for the USRP X440 I am facing an issue:
To start the whole process, I cloned \[1\] and added my own module with rfnoc_modtool, which worked. Then I added the IP core as .xci file into /rfnoc/fpga/oot-blocks/ip/Demodulat_ip_0 and icores/x440_X4_400_rfnoc_image_core_demodchest.yml I created the folder /build and executed make, sudo make install and make x440_X4_400_rfnoc_image_core_demodchest as explained in \[2\]. As soon as the IP generation starts, I face the following issue: ``` WARNING: [IP_Flow 19-2162] IP 'Demodulat_ip_0' is locked: ``` ``` CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/peter/git/rfnoc-oot-blocks/build/build-ip/xczu28drffvg1517-2e/Demodulat_ip_0/Demodulat_ip_0.xci ``` ``` CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/peter/git/rfnoc-oot-blocks/build/build-ip/xczu28drffvg1517-2e/Demodulat_ip_0/Demodulat_ip_0.xci ``` ``` [00:00:04] Current task: Initialization +++ Current Phase: Finished ``` ``` [00:00:04] Executing Tcl: synth_design -top Demodulat_ip_0 -part xczu28dr-ffvg1517-2-e -mode out_of_context ``` ``` [00:00:04] Starting Synthesis Command ``` ``` WARNING: [IP_Flow 19-2162] IP 'Demodulat_ip_0' is locked: ``` ``` ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified ``` ``` ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ``` ``` ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ``` ``` ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ``` ``` ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ``` ``` ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ``` ``` ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ``` ``` [00:00:05] Current task: Synthesis +++ Current Phase: Starting ``` ``` ERROR: [Vivado 12-398] No designs are open ``` ``` [00:00:05] Current task: Synthesis +++ Current Phase: Finished ``` ``` [00:00:05] Process terminated. Status: Failure ``` ``` ======================================================== ``` ``` Warnings: 2 ``` ``` Critical Warnings: 2 ``` Errors: 8 I am aware of the FAQ \[3\] - however if I run *source setupenv.sh* I will get: ``` Setting up a 64-bit FPGA build environment for the USRP-X4xx... ``` ``` - Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin) ``` ``` Installed version is Vivado v2021.1_AR76780 (64-bit) ``` ``` Environment successfully initialized. ``` In the .xci file of the IP core in l. 64, it says: "RUNTIME_PARAM.SWVERSION">2021.1_AR76780 It seems, that the issue doesn’t come from a Vivado version mismatch. I’ve uploaded the code to [https://github.com/gu-peter/rfnoc-oot-blocks](https://github.com/gu-peter/rfnoc-oot-blocks "repository") It would be wonderful if someone can give me a hint! E.g. if its rather a RFNoC or a Xilinx issue. Best regards, Peter --- \[1\] https://github.com/EttusResearch/rfnoc-oot-blocks \[2\] https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0#Example:_Adding_an_FFT_Block \[3\] https://kb.ettus.com/RFNoC_Frequently_Asked_Questions
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