Hello, I am working with RFNoC and trying to better understand how sample data is actually delivered over CHDR after the Radio + DDC block, particularly in terms of **packet spacing vs. bus rate**.
My assumption is: * The RF chain (Radio + DDC) outputs samples at a configured sample rate, e.g., 250 KHz. * RFNoC groups samples into packets of SPP samples (for example, 64 samples per CHDR packet). * When a packet is produced, it is transmitted across the RFNoC fabric at the **fabric clock rate** (e.g., 200 MHz), meaning the packet data appears as a short **burst** of consecutive valid cycles. * After that burst, there is a gap (idle time) until enough samples are accumulated to form the next packet. So, for example, at: * Fs = 250 kS/s * SPP = 64 Then we would expect: * One packet every 64 / 250k = 256 µs * Packet burst duration = 64 cycles at 200 MHz ≈ 320 ns * Approximately 256 µs – 320 ns of idle time before the next packet. ### My questions are: 1. Is this understanding correct? 2. Is RFNoC guaranteed to behave this way, or can buffering cause multiple packets to be sent back-to-back with no idle gap? 3. Is there any official documentation describing packetization timing behavior of Radio/DDC RFNoC fabric? Thanks in advance!
_______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
