On Tue, May 5, 2026 at 5:42 PM Eugene Grayver <[email protected]> wrote:
> Hi, > > I have an application that needs 2 GHz of bandwidth. I only need one > channel. How hard would it be to change the max sample rate? Is the FPGA > barely meeting timing? > The RFDC is set up to output 8 samples/clock (the maximum that the core supports). That would mean for 2 GHz of total samples coming out from the core, you'll have to run with a 250 MHz clock - very doable in the RFSoC. Note the DDR interface clock runs at 300 MHz, and there is a bus clock that is 266.67 MHz somewhere in there, too. A current design I am working with utilizes the DDR clock extensively and runs most of the DSP in that domain. The bigger issue might be that the RF front end is set up to do real sampling, and the maximum rate is 4.096 Msps for each ADC. You can set it up to be a shifted/decimated 2 GHz of BW, but anything above that 2 GHz Nyquist externally needs to be filtered extremely well to avoid any analog aliases that come in. > > Also, do we need a license for the 100 GbE MAC core? I saw a warning to > that effect when building a custom image but as far as I know the 100 GbE > MAC is free. > The 100Gbe Hard IP MAC is free but you may still need to request a license from AMD. Good luck. Brian
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