Author: [email protected]
Date: Tue May 12 14:35:43 2009
New Revision: 1923
Modified:
branches/bleeding_edge/src/arm/assembler-arm.cc
Log:
Fix incorrect assert on ARM that assumed that coprocessor id was always
zero. This
is hit in debug mode on non-EABI non-simulator ARM platforms. Thanks to
[email protected] for reporting.
Review URL: http://codereview.chromium.org/113299
Modified: branches/bleeding_edge/src/arm/assembler-arm.cc
==============================================================================
--- branches/bleeding_edge/src/arm/assembler-arm.cc (original)
+++ branches/bleeding_edge/src/arm/assembler-arm.cc Tue May 12 14:35:43 2009
@@ -211,6 +211,7 @@
// Instruction bit masks
RdMask = 15 << 12, // in str instruction
CondMask = 15 << 28,
+ CoprocessorMask = 15 << 8,
OpCodeMask = 15 << 21, // in data-processing instructions
Imm24Mask = (1 << 24) - 1,
Off12Mask = (1 << 12) - 1,
@@ -616,7 +617,8 @@
void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {
// unindexed addressing is not encoded by this function
- ASSERT((instr & ~(CondMask | P | U | N | W | L)) == (B27 | B26));
+ ASSERT_EQ((B27 | B26),
+ (instr & ~(CondMask | CoprocessorMask | P | U | N | W | L)));
ASSERT(x.rn_.is_valid() && !x.rm_.is_valid());
int am = x.am_;
int offset_8 = x.offset_;
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