Reviewers: paul.l...,
Message:
I had one more issue in macroassembler-mips.cc. Switched t8 usage to t9
https://codereview.chromium.org/1323763002/diff/1/src/compiler/mips/code-generator-mips.cc
File src/compiler/mips/code-generator-mips.cc (right):
https://codereview.chromium.org/1323763002/diff/1/src/compiler/mips/code-generator-mips.cc#newcode308
src/compiler/mips/code-generator-mips.cc:308: __ asm_instr(result,
MemOperand(t8, 0)); \
On 2015/08/31 22:56:34, paul.l... wrote:
I think these temp regs should be kScratchReg or possibly
kScratchReg2. t8 is
reserved for macro-assembler, and we should probably preserve that
layering.
Also note that Assembler::sdc1() now uses t8 as a 2nd temporary. I
think that
usage would still work, since we would only overwrite t8 after we have
the
address, but it seems a bit fragile.
Done.
https://codereview.chromium.org/1323763002/diff/1/src/compiler/mips64/code-generator-mips64.cc
File src/compiler/mips64/code-generator-mips64.cc (right):
https://codereview.chromium.org/1323763002/diff/1/src/compiler/mips64/code-generator-mips64.cc#newcode309
src/compiler/mips64/code-generator-mips64.cc:309: __ asm_instr(result,
MemOperand(t8, 0)); \
On 2015/08/31 22:56:34, paul.l... wrote:
I think these temp regs should be kScratchReg or possibly
kScratchReg2. t8 is
reserved for macro-assembler, and we should probably preserve that
layering.
Done.
https://codereview.chromium.org/1323763002/diff/1/src/mips/assembler-mips.cc
File src/mips/assembler-mips.cc (right):
https://codereview.chromium.org/1323763002/diff/1/src/mips/assembler-mips.cc#newcode2027
src/mips/assembler-mips.cc:2027: CHECK(!src.rm().is(at));
On 2015/08/31 22:56:34, paul.l... wrote:
I think these should be DCHECK (here and below).
Done.
https://codereview.chromium.org/1323763002/diff/1/src/mips/assembler-mips.cc#newcode2084
src/mips/assembler-mips.cc:2084: mfhc1(t8, fd);
On 2015/08/31 22:56:34, paul.l... wrote:
Note the use of t8 here. (t8 is reserved for macro-assembler use, but
this is
probably ok, as ldc1 and sdc1 _should_ be moved to macro-assembler
anyway (as
Ldc1() and Sdc1(), I will create an issue for that.)
It might make sense to add another DCHECK within this block:
DCHECK(!src.rm().is(t8));
Done.
https://codereview.chromium.org/1323763002/diff/1/src/mips64/assembler-mips64.cc
File src/mips64/assembler-mips64.cc (right):
https://codereview.chromium.org/1323763002/diff/1/src/mips64/assembler-mips64.cc#newcode2379
src/mips64/assembler-mips64.cc:2379: CHECK(!src.rm().is(at));
On 2015/08/31 22:56:34, paul.l... wrote:
DCHECK() here and below.
Done.
Description:
MIPS: Fix illegal use of at register
Fix illegal use of at register when ldc1 and sdc1 are called. Added dchecks
to
prevent such a usage.
TEST=mjsunit/asm/float64array-negative-offset(r6),
mjsunit/asm/float64array-outofbounds(r6)
Please review this at https://codereview.chromium.org/1323763002/
Base URL: https://chromium.googlesource.com/v8/v8.git@master
Affected files (+28, -20 lines):
M src/compiler/mips/code-generator-mips.cc
M src/compiler/mips64/code-generator-mips64.cc
M src/mips/assembler-mips.cc
M src/mips/lithium-codegen-mips.cc
M src/mips/macro-assembler-mips.cc
M src/mips64/assembler-mips64.cc
Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc
b/src/compiler/mips/code-generator-mips.cc
index
7d9f204c6443ffe27f20c5b30cdd58be831f76f7..7769b9e739ec5873e47b32a0e9060082e7350e5e
100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -304,8 +304,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
if (instr->InputAt(0)->IsRegister())
{ \
auto offset =
i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset,
i.InputOperand(1)); \
- __ addu(at, i.InputRegister(2),
offset); \
- __ asm_instr(result, MemOperand(at,
0)); \
+ __ addu(kScratchReg, i.InputRegister(2),
offset); \
+ __ asm_instr(result, MemOperand(kScratchReg,
0)); \
} else
{ \
auto offset =
i.InputOperand(0).immediate(); \
__ Branch(ool->entry(), ls, i.InputRegister(1),
Operand(offset)); \
@@ -322,8 +322,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
if (instr->InputAt(0)->IsRegister())
{ \
auto offset =
i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset,
i.InputOperand(1)); \
- __ addu(at, i.InputRegister(2),
offset); \
- __ asm_instr(result, MemOperand(at,
0)); \
+ __ addu(kScratchReg, i.InputRegister(2),
offset); \
+ __ asm_instr(result, MemOperand(kScratchReg,
0)); \
} else
{ \
auto offset =
i.InputOperand(0).immediate(); \
__ Branch(ool->entry(), ls, i.InputRegister(1),
Operand(offset)); \
@@ -340,8 +340,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
auto offset = i.InputRegister(0); \
auto value = i.Input##width##Register(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
- __ addu(at, i.InputRegister(3), offset); \
- __ asm_instr(value, MemOperand(at, 0)); \
+ __ addu(kScratchReg, i.InputRegister(3), offset); \
+ __ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
auto value = i.Input##width##Register(2); \
@@ -359,8 +359,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
auto offset = i.InputRegister(0); \
auto value = i.InputRegister(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
- __ addu(at, i.InputRegister(3), offset); \
- __ asm_instr(value, MemOperand(at, 0)); \
+ __ addu(kScratchReg, i.InputRegister(3), offset); \
+ __ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
auto offset = i.InputOperand(0).immediate(); \
auto value = i.InputRegister(2); \
Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc
b/src/compiler/mips64/code-generator-mips64.cc
index
da2fce31acaa4fb3bf01d9065117493aa75ac9d2..debca20ca31bfe83b69c33237f5ccd9b1f99caf3
100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -305,8 +305,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
if (instr->InputAt(0)->IsRegister())
{ \
auto offset =
i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset,
i.InputOperand(1)); \
- __ Daddu(at, i.InputRegister(2),
offset); \
- __ asm_instr(result, MemOperand(at,
0)); \
+ __ Daddu(kScratchReg, i.InputRegister(2),
offset); \
+ __ asm_instr(result, MemOperand(kScratchReg,
0)); \
} else
{ \
int offset =
static_cast<int>(i.InputOperand(0).immediate()); \
__ Branch(ool->entry(), ls, i.InputRegister(1),
Operand(offset)); \
@@ -323,8 +323,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
if (instr->InputAt(0)->IsRegister())
{ \
auto offset =
i.InputRegister(0); \
__ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset,
i.InputOperand(1)); \
- __ Daddu(at, i.InputRegister(2),
offset); \
- __ asm_instr(result, MemOperand(at,
0)); \
+ __ Daddu(kScratchReg, i.InputRegister(2),
offset); \
+ __ asm_instr(result, MemOperand(kScratchReg,
0)); \
} else
{ \
int offset =
static_cast<int>(i.InputOperand(0).immediate()); \
__ Branch(ool->entry(), ls, i.InputRegister(1),
Operand(offset)); \
@@ -341,8 +341,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
auto offset = i.InputRegister(0); \
auto value = i.Input##width##Register(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
- __ Daddu(at, i.InputRegister(3), offset); \
- __ asm_instr(value, MemOperand(at, 0)); \
+ __ Daddu(kScratchReg, i.InputRegister(3), offset); \
+ __ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
int offset = static_cast<int>(i.InputOperand(0).immediate()); \
auto value = i.Input##width##Register(2); \
@@ -360,8 +360,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool&
predicate,
auto offset = i.InputRegister(0); \
auto value = i.InputRegister(2); \
__ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
- __ Daddu(at, i.InputRegister(3), offset); \
- __ asm_instr(value, MemOperand(at, 0)); \
+ __ Daddu(kScratchReg, i.InputRegister(3), offset); \
+ __ asm_instr(value, MemOperand(kScratchReg, 0)); \
} else { \
int offset = static_cast<int>(i.InputOperand(0).immediate()); \
auto value = i.InputRegister(2); \
Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index
783d311b8b720f0eec2c520b3017faee46d17746..ce6f278540fd30f2095130a3555b16b7c6248680
100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -2026,6 +2026,8 @@ void Assembler::lwc1(FPURegister fd, const
MemOperand& src) {
void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// load to two 32-bit loads.
+ DCHECK(!src.rm().is(at));
+ DCHECK(!src.rm().is(t8));
if (IsFp64Mode()) {
if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
GenInstrImmediate(LWC1, src.rm(), fd,
@@ -2071,6 +2073,8 @@ void Assembler::swc1(FPURegister fd, const
MemOperand& src) {
void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// store to two 32-bit stores.
+ DCHECK(!src.rm().is(at));
+ DCHECK(!src.rm().is(t8));
if (IsFp64Mode()) {
if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
GenInstrImmediate(SWC1, src.rm(), fd,
Index: src/mips/lithium-codegen-mips.cc
diff --git a/src/mips/lithium-codegen-mips.cc
b/src/mips/lithium-codegen-mips.cc
index
5586ed1ab264e7dd1f1a68ed40a313ff71e370e3..9f0c8f5f3946d18fea7f01084fec0a9b0fdce911
100644
--- a/src/mips/lithium-codegen-mips.cc
+++ b/src/mips/lithium-codegen-mips.cc
@@ -4193,6 +4193,7 @@ void
LCodeGen::DoStoreKeyedFixedDoubleArray(LStoreKeyed* instr) {
DoubleRegister value = ToDoubleRegister(instr->value());
Register elements = ToRegister(instr->elements());
Register scratch = scratch0();
+ Register scratch_1 = scratch1();
DoubleRegister double_scratch = double_scratch0();
bool key_is_constant = instr->key()->IsConstantOperand();
int base_offset = instr->base_offset();
@@ -4224,8 +4225,9 @@ void
LCodeGen::DoStoreKeyedFixedDoubleArray(LStoreKeyed* instr) {
// Only load canonical NaN if the comparison above set the overflow.
__ bind(&is_nan);
- __ LoadRoot(at, Heap::kNanValueRootIndex);
- __ ldc1(double_scratch, FieldMemOperand(at, HeapNumber::kValueOffset));
+ __ LoadRoot(scratch_1, Heap::kNanValueRootIndex);
+ __ ldc1(double_scratch,
+ FieldMemOperand(scratch_1, HeapNumber::kValueOffset));
__ sdc1(double_scratch, MemOperand(scratch, 0));
__ Branch(&done);
}
Index: src/mips/macro-assembler-mips.cc
diff --git a/src/mips/macro-assembler-mips.cc
b/src/mips/macro-assembler-mips.cc
index
9ba814ae2ff85887350cd57c7d0cbe739834f1a1..a19fdc4b3a49f709199b080b751276d5740859bd
100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -4939,10 +4939,10 @@ void MacroAssembler::LeaveExitFrame(bool
save_doubles, Register argument_count,
// Optionally restore all double registers.
if (save_doubles) {
// Remember: we only need to restore every 2nd double FPU value.
- lw(t8, MemOperand(fp, ExitFrameConstants::kSPOffset));
+ lw(t9, MemOperand(fp, ExitFrameConstants::kSPOffset));
for (int i = 0; i < FPURegister::kMaxNumRegisters; i+=2) {
FPURegister reg = FPURegister::from_code(i);
- ldc1(reg, MemOperand(t8, i * kDoubleSize + kPointerSize));
+ ldc1(reg, MemOperand(t9, i * kDoubleSize + kPointerSize));
}
}
Index: src/mips64/assembler-mips64.cc
diff --git a/src/mips64/assembler-mips64.cc b/src/mips64/assembler-mips64.cc
index
a7a8d6d511d22c9f1e00dce5af4b46e583dbe269..5837e6dcf96454af0e3f720f96e14e6d573f76e3
100644
--- a/src/mips64/assembler-mips64.cc
+++ b/src/mips64/assembler-mips64.cc
@@ -2378,6 +2378,7 @@ void Assembler::lwc1(FPURegister fd, const
MemOperand& src) {
void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
+ DCHECK(!src.rm().is(at));
if (is_int16(src.offset_)) {
GenInstrImmediate(LDC1, src.rm(), fd, src.offset_);
} else { // Offset > 16 bits, use multiple instructions to load.
@@ -2398,6 +2399,7 @@ void Assembler::swc1(FPURegister fd, const
MemOperand& src) {
void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
+ DCHECK(!src.rm().is(at));
if (is_int16(src.offset_)) {
GenInstrImmediate(SDC1, src.rm(), fd, src.offset_);
} else { // Offset > 16 bits, use multiple instructions to load.
--
--
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