[v8-dev] Implemented missing instructions in ia32 and x64 disassembler.... (issue3471011)

[kaznacheev]

Reviewers: Lasse Reichstein,

Message:
Hi Lasse,
While debugging r5515 (dec_b support to ia32 and x64 disassembler) I noticed
quite a few "Unimplemented instruction" lines in the code.

I fixed that (at least nothing unimplemented shows up for sunspider tests).

Please take a look, I might be doing something not quite optimal.

Description:
Implemented missing instructions in ia32 and x64 disassembler.

ia32: fld(i), fldpi
x64: fld(i), fldpi, cvtsd2si, cvttsd2si


Please review this at http://codereview.chromium.org/3471011/show

SVN Base: http://v8.googlecode.com/svn/branches/bleeding_edge/

Affected files:
  M     src/ia32/disasm-ia32.cc
  M     src/x64/disasm-x64.cc
  M     test/cctest/test-disasm-ia32.cc


Index: src/ia32/disasm-ia32.cc
===================================================================
--- src/ia32/disasm-ia32.cc     (revision 5515)
+++ src/ia32/disasm-ia32.cc     (working copy)
@@ -718,6 +718,10 @@

     case 0xD9:
       switch (modrm_byte & 0xF8) {
+        case 0xC0:
+          mnem = "fld";
+          has_register = true;
+          break;
         case 0xC8:
           mnem = "fxch";
           has_register = true;
Index: src/x64/disasm-x64.cc
===================================================================
--- src/x64/disasm-x64.cc       (revision 5515)
+++ src/x64/disasm-x64.cc       (working copy)
@@ -891,6 +891,10 @@

     case 0xD9:
       switch (modrm_byte & 0xF8) {
+        case 0xC0:
+          mnem = "fld";
+          has_register = true;
+          break;
         case 0xC8:
           mnem = "fxch";
           has_register = true;
@@ -901,6 +905,7 @@
             case 0xE1: mnem = "fabs"; break;
             case 0xE4: mnem = "ftst"; break;
             case 0xE8: mnem = "fld1"; break;
+            case 0xEB: mnem = "fldpi"; break;
             case 0xEE: mnem = "fldz"; break;
             case 0xF5: mnem = "fprem1"; break;
             case 0xF7: mnem = "fincstp"; break;
@@ -1059,6 +1064,21 @@
       get_modrm(*current, &mod, &regop, &rm);
       AppendToBuffer("%sd %s,", mnemonic, NameOfXMMRegister(regop));
       current += PrintRightOperand(current);
+    } else if (opcode == 0x2C) {
+      // CVTTSD2SI:
+      // Convert with truncation scalar double-precision FP to integer.
+      int mod, regop, rm;
+      get_modrm(*current, &mod, &regop, &rm);
+      AppendToBuffer("cvttsd2si%c %s,",
+          operand_size_code(), NameOfCPURegister(regop));
+      current += PrintRightXMMOperand(current);
+    } else if (opcode == 0x2D) {
+      // CVTSD2SI: Convert scalar double-precision FP to integer.
+      int mod, regop, rm;
+      get_modrm(*current, &mod, &regop, &rm);
+      AppendToBuffer("cvtsd2si%c %s,",
+          operand_size_code(), NameOfCPURegister(regop));
+      current += PrintRightXMMOperand(current);
     } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
       // XMM arithmetic. Mnemonic was retrieved at the start of this  
function.
       int mod, regop, rm;
@@ -1089,11 +1109,14 @@
       AppendToBuffer("%ss %s,", mnemonic, NameOfXMMRegister(regop));
       current += PrintRightOperand(current);
     } else if (opcode == 0x2C) {
-      // CVTTSS2SI: Convert scalar single-precision FP to dword integer.
+      // CVTTSS2SI:
+      // Convert with truncation scalar single-precision FP to dword  
integer.
       // Assert that mod is not 3, so source is memory, not an XMM  
register.
       ASSERT_NE(0xC0, *current & 0xC0);
       current += PrintOperands("cvttss2si", REG_OPER_OP_ORDER, current);
     } else if (opcode == 0x5A) {
+      // CVTSS2SD:
+      // Convert scalar single-precision FP to scalar double-precision FP.
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
       AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop));
Index: test/cctest/test-disasm-ia32.cc
===================================================================
--- test/cctest/test-disasm-ia32.cc     (revision 5515)
+++ test/cctest/test-disasm-ia32.cc     (working copy)
@@ -336,8 +336,10 @@
   // 0xD9 instructions
   __ nop();

+  __ fld(1);
   __ fld1();
   __ fldz();
+  __ fldpi();
   __ fabs();
   __ fchs();
   __ fprem();


--
v8-dev mailing list
v8-dev@googlegroups.com
http://groups.google.com/group/v8-dev