Revision: 18834
Author: [email protected]
Date: Fri Jan 24 15:58:36 2014 UTC
Log: A64: Add LGetCachedArrayIndex and LHasCachedArrayIndexAndBranch
BUG=none
[email protected]
Review URL: https://codereview.chromium.org/146893002
http://code.google.com/p/v8/source/detail?r=18834
Modified:
/branches/experimental/a64/src/a64/lithium-a64.cc
/branches/experimental/a64/src/a64/lithium-a64.h
/branches/experimental/a64/src/a64/lithium-codegen-a64.cc
=======================================
--- /branches/experimental/a64/src/a64/lithium-a64.cc Fri Jan 24 14:09:40
2014 UTC
+++ /branches/experimental/a64/src/a64/lithium-a64.cc Fri Jan 24 15:58:36
2014 UTC
@@ -129,6 +129,13 @@
right()->PrintTo(stream);
stream->Add(" then B%d else B%d", true_block_id(), false_block_id());
}
+
+
+void LHasCachedArrayIndexAndBranch::PrintDataTo(StringStream* stream) {
+ stream->Add("if has_cached_array_index(");
+ value()->PrintTo(stream);
+ stream->Add(") then B%d else B%d", true_block_id(), false_block_id());
+}
bool LGoto::HasInterestingComment(LCodeGen* gen) const {
@@ -1457,7 +1464,9 @@
LInstruction* LChunkBuilder::DoGetCachedArrayIndex(
HGetCachedArrayIndex* instr) {
- UNIMPLEMENTED_INSTRUCTION();
+ ASSERT(instr->value()->representation().IsTagged());
+ LOperand* value = UseRegisterAtStart(instr->value());
+ return DefineAsRegister(new(zone()) LGetCachedArrayIndex(value));
}
@@ -1480,7 +1489,9 @@
LInstruction* LChunkBuilder::DoHasCachedArrayIndexAndBranch(
HHasCachedArrayIndexAndBranch* instr) {
- UNIMPLEMENTED_INSTRUCTION();
+ ASSERT(instr->value()->representation().IsTagged());
+ return new(zone()) LHasCachedArrayIndexAndBranch(
+ UseRegisterAtStart(instr->value()), TempRegister());
}
=======================================
--- /branches/experimental/a64/src/a64/lithium-a64.h Fri Jan 24 14:09:40
2014 UTC
+++ /branches/experimental/a64/src/a64/lithium-a64.h Fri Jan 24 15:58:36
2014 UTC
@@ -103,9 +103,11 @@
V(ForInCacheArray) \
V(ForInPrepareMap) \
V(FunctionLiteral) \
+ V(GetCachedArrayIndex) \
V(GlobalObject) \
V(GlobalReceiver) \
V(Goto) \
+ V(HasCachedArrayIndexAndBranch) \
V(HasInstanceTypeAndBranch) \
V(In) \
V(InnerAllocatedObject) \
@@ -1294,6 +1296,19 @@
};
+class LGetCachedArrayIndex: public LTemplateInstruction<1, 1, 0> {
+ public:
+ explicit LGetCachedArrayIndex(LOperand* value) {
+ inputs_[0] = value;
+ }
+
+ LOperand* value() { return inputs_[0]; }
+
+
DECLARE_CONCRETE_INSTRUCTION(GetCachedArrayIndex, "get-cached-array-index")
+ DECLARE_HYDROGEN_ACCESSOR(GetCachedArrayIndex)
+};
+
+
class LGlobalObject: public LTemplateInstruction<1, 1, 0> {
public:
explicit LGlobalObject(LOperand* context) {
@@ -1318,6 +1333,24 @@
};
+class LHasCachedArrayIndexAndBranch: public LControlInstruction<1, 1> {
+ public:
+ LHasCachedArrayIndexAndBranch(LOperand* value, LOperand* temp) {
+ inputs_[0] = value;
+ temps_[0] = temp;
+ }
+
+ LOperand* value() { return inputs_[0]; }
+ LOperand* temp() { return temps_[0]; }
+
+ DECLARE_CONCRETE_INSTRUCTION(HasCachedArrayIndexAndBranch,
+ "has-cached-array-index-and-branch")
+ DECLARE_HYDROGEN_ACCESSOR(HasCachedArrayIndexAndBranch)
+
+ virtual void PrintDataTo(StringStream* stream);
+};
+
+
class LHasInstanceTypeAndBranch: public LControlInstruction<1, 1> {
public:
LHasInstanceTypeAndBranch(LOperand* value, LOperand* temp) {
=======================================
--- /branches/experimental/a64/src/a64/lithium-codegen-a64.cc Fri Jan 24
15:42:18 2014 UTC
+++ /branches/experimental/a64/src/a64/lithium-codegen-a64.cc Fri Jan 24
15:58:36 2014 UTC
@@ -2678,6 +2678,19 @@
__ Bind(&use_cache);
}
+
+
+void LCodeGen::DoGetCachedArrayIndex(LGetCachedArrayIndex* instr) {
+ Register input = ToRegister(instr->value());
+ Register result = ToRegister(instr->result());
+
+ __ AssertString(input);
+
+ // Assert that we can use a W register load to get the hash.
+ ASSERT((String::kHashShift + String::kArrayIndexValueBits) < kWRegSize);
+ __ Ldr(result.W(), FieldMemOperand(input, String::kHashFieldOffset));
+ __ IndexFromHash(result, result);
+}
void LCodeGen::DoGlobalObject(LGlobalObject* instr) {
@@ -2712,6 +2725,19 @@
void LCodeGen::DoGoto(LGoto* instr) {
EmitGoto(instr->block_id());
}
+
+
+void LCodeGen::DoHasCachedArrayIndexAndBranch(
+ LHasCachedArrayIndexAndBranch* instr) {
+ Register input = ToRegister(instr->value());
+ Register temp = ToRegister32(instr->temp());
+
+ // Assert that the cache status bits fit in a W register.
+ ASSERT(is_uint32(String::kContainsCachedArrayIndexMask));
+ __ Ldr(temp, FieldMemOperand(input, String::kHashFieldOffset));
+ __ Tst(temp, String::kContainsCachedArrayIndexMask);
+ EmitBranch(instr, eq);
+}
// HHasInstanceTypeAndBranch instruction is built with an interval of type
--
--
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