[v8-dev] ARM64 simulator fix for EXTR (issue 286193004)

[frkoenig via v8-dev]

Reviewers: Sven Panne, Rodolph Perfetta (ARM), jbramley,
Description:
ARM64 simulator fix for EXTR

Fixes extract when imms = 0 because a left shift of 64 is not valid.

Please review this at https://codereview.chromium.org/286193004/

SVN Base: https://v8.googlecode.com/svn/branches/bleeding_edge

Affected files (+24, -18 lines):
  M src/arm64/simulator-arm64.cc
  M test/cctest/test-assembler-arm64.cc


Index: src/arm64/simulator-arm64.cc
diff --git a/src/arm64/simulator-arm64.cc b/src/arm64/simulator-arm64.cc
index  
c7c9f6cedd9105aef766f45f273dfcf8226d9fc1..1ae57e9e2f1fcedba8cd1db7d3eb55e1372cde59  
100644
--- a/src/arm64/simulator-arm64.cc
+++ b/src/arm64/simulator-arm64.cc
@@ -2103,10 +2103,12 @@ void Simulator::VisitExtract(Instruction* instr) {
   unsigned lsb = instr->ImmS();
   unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
                                                     : kWRegSizeInBits;
-  set_reg(reg_size,
-          instr->Rd(),
-          (static_cast<uint64_t>(reg(reg_size, instr->Rm())) >> lsb) |
-          (reg(reg_size, instr->Rn()) << (reg_size - lsb)));
+  uint64_t result = reg(reg_size, instr->Rm());
+  if (lsb) {
+    result = (result >> lsb) | (reg(reg_size, instr->Rn()) << (reg_size -  
lsb));
+  }
+
+  set_reg(reg_size, instr->Rd(), result);
 }


Index: test/cctest/test-assembler-arm64.cc
diff --git a/test/cctest/test-assembler-arm64.cc  
b/test/cctest/test-assembler-arm64.cc
index  
c89cccef7ff62023a35311f0a3347012b0357d7e..6550ad0cf9e167409d6b9f17fa75ce4f330edd2b  
100644
--- a/test/cctest/test-assembler-arm64.cc
+++ b/test/cctest/test-assembler-arm64.cc
@@ -4893,26 +4893,30 @@ TEST(extr) {
   __ Mov(x2, 0xfedcba9876543210L);

   __ Extr(w10, w1, w2, 0);
-  __ Extr(w11, w1, w2, 1);
-  __ Extr(x12, x2, x1, 2);
+  __ Extr(x11, x1, x2, 0);
+  __ Extr(w12, w1, w2, 1);
+  __ Extr(x13, x2, x1, 2);

-  __ Ror(w13, w1, 0);
-  __ Ror(w14, w2, 17);
-  __ Ror(w15, w1, 31);
-  __ Ror(x18, x2, 1);
-  __ Ror(x19, x1, 63);
+  __ Ror(w20, w1, 0);
+  __ Ror(x21, x1, 0);
+  __ Ror(w22, w2, 17);
+  __ Ror(w23, w1, 31);
+  __ Ror(x24, x2, 1);
+  __ Ror(x25, x1, 63);
   END();

   RUN();

   ASSERT_EQUAL_64(0x76543210, x10);
-  ASSERT_EQUAL_64(0xbb2a1908, x11);
-  ASSERT_EQUAL_64(0x0048d159e26af37bUL, x12);
-  ASSERT_EQUAL_64(0x89abcdef, x13);
-  ASSERT_EQUAL_64(0x19083b2a, x14);
-  ASSERT_EQUAL_64(0x13579bdf, x15);
-  ASSERT_EQUAL_64(0x7f6e5d4c3b2a1908UL, x18);
-  ASSERT_EQUAL_64(0x02468acf13579bdeUL, x19);
+  ASSERT_EQUAL_64(0xfedcba9876543210L, x11);
+  ASSERT_EQUAL_64(0xbb2a1908, x12);
+  ASSERT_EQUAL_64(0x0048d159e26af37bUL, x13);
+  ASSERT_EQUAL_64(0x89abcdef, x20);
+  ASSERT_EQUAL_64(0x0123456789abcdefL, x21);
+  ASSERT_EQUAL_64(0x19083b2a, x22);
+  ASSERT_EQUAL_64(0x13579bdf, x23);
+  ASSERT_EQUAL_64(0x7f6e5d4c3b2a1908UL, x24);
+  ASSERT_EQUAL_64(0x02468acf13579bdeUL, x25);

   TEARDOWN();
 }


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