Reviewers: jochen traveling until Jun 23,
Description:
v8 atomicops: Drop SSE2 detection, v8 always requires SSE2.
This ports Chromium's https://codereview.chromium.org/291993003/
BUG=chromium:348761, chromium:94925
LOG=N
Please review this at https://codereview.chromium.org/345443003/
SVN Base: http://v8.googlecode.com/svn/branches/bleeding_edge/
Affected files (+0, -31 lines):
M src/base/atomicops_internals_x86_gcc.h
M src/base/atomicops_internals_x86_gcc.cc
Index: src/base/atomicops_internals_x86_gcc.cc
===================================================================
--- src/base/atomicops_internals_x86_gcc.cc (revision 21880)
+++ src/base/atomicops_internals_x86_gcc.cc (working copy)
@@ -42,7 +42,6 @@
// default values should hopefully be pretty safe.
struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
false, // bug can't exist before process spawns multiple threads
- false, // no SSE2
};
} } // namespace v8::base
@@ -88,9 +87,6 @@
} else {
AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
}
-
- // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
- AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
}
class AtomicOpsx86Initializer {
Index: src/base/atomicops_internals_x86_gcc.h
===================================================================
--- src/base/atomicops_internals_x86_gcc.h (revision 21880)
+++ src/base/atomicops_internals_x86_gcc.h (working copy)
@@ -17,7 +17,6 @@
struct AtomicOps_x86CPUFeatureStruct {
bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do
lfence
// after acquire compare-and-swap.
- bool has_sse2; // Processor has SSE2.
};
extern struct AtomicOps_x86CPUFeatureStruct
AtomicOps_Internalx86CPUFeatures;
@@ -92,10 +91,6 @@
*ptr = value;
}
-#if defined(__x86_64__)
-
-// 64-bit implementations of memory barrier can be simpler, because it
-// "mfence" is guaranteed to exist.
inline void MemoryBarrier() {
__asm__ __volatile__("mfence" : : : "memory");
}
@@ -105,28 +100,6 @@
MemoryBarrier();
}
-#else
-
-inline void MemoryBarrier() {
- if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
- __asm__ __volatile__("mfence" : : : "memory");
- } else { // mfence is faster but not present on PIII
- Atomic32 x = 0;
- NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
- }
-}
-
-inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
- if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
- *ptr = value;
- __asm__ __volatile__("mfence" : : : "memory");
- } else {
- NoBarrier_AtomicExchange(ptr, value);
- // acts as a barrier on PIII
- }
-}
-#endif
-
inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
ATOMICOPS_COMPILER_BARRIER();
*ptr = value; // An x86 store acts as a release barrier.
--
--
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