On Monday 29 June 2009, khaled wrote: > I'm using an AMD Opteron 4 cores, I Want to have the TLB and the L3 > cache misses > so I had used valgrind with callgrind option but I had just the L1 & L2 > caches misses > > is there any option with the valgrind tools to have the TLB and the L3 > cache misses ???
The cache model of Cachegrind/Callgrind does not simulate TLBs. To see the L3 behavior, you could specify the L3 parameters (size/associativity/linesize) for Cachegrinds/Callgrind L2. However: * Cachegrinds/Callgrinds cache model is inclusive, while AMDs caches are exclusive (L2/L3 are victim caches). This will lead to some differences. * L3 on AMDs 4-cores is shared, so the scenario for the simulation assumes that all other cores are idle. You could add a wishlist as bug report. Josef > > thank you so much > ------------------------------------------------------------------------------ _______________________________________________ Valgrind-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/valgrind-users
