On Friday 11 February 2011, Jain, Keerti wrote: > Can anyone let me know that can calgrind/cachegrind is able to simulate > the Nehalem(Intel Xeon 54xx/55xx) cache architecture? > As Nehalem has a large L2 cache.
I do not see the connection between your question and that statement. Cache hierarchies in real processors are quite more complex than the cache model of Callgrind/Cachegrind (e.g. they work asynchronous, with multiple loads on the fly, and have a kinds of prefetchers doing future access predictions). Thus, this is always only an approximation. Nehalem has 3 cache levels. Private L1I,L1D and L2 per core, and shared L3. Callgrind/Cachegrind always simulate 2 levels only. When it detects a processor with 3 levels, it uses the parameters for L1 and L3. So, what you miss is how many of the L1 misses actually are L2 hits. But L1 hits/misses and LL misses should be reasonable approximations to Nehalems behaviour. The latter (main memory accesses) matters most for performance. Josef > > With regards, > Keerti > > =============================================================================== > > Please access the attached hyperlink for an important electronic > communications disclaimer: > http://www.credit-suisse.com/legal/en/disclaimer_email_ib.html > =============================================================================== > > > ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Valgrind-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/valgrind-users
