On 23/01/12 21:31, Daniel Mierswa wrote: > On 23.01.2012 22:16, Tom Hughes wrote: >> Well that is an AVX instruction, but I thought they were only valid in 64 >> bit mode as 0xC5 is (as John said) LDS in 32 bit mode. In 64 bit mode it is >> a VEX prefix for an AVX instruction. > Ok interesting. Does that mean my gcc produces bad code or is your assumption > wrong or something else? :P
Further investigation suggests that AVX instructions are valid in 32 bit mode and the VEX prefix encoding has been carefully arranged so that valid prefixes cannot be mistaken for valid LDS instructions. See http://aceshardware.freeforums.org/intel-avx-kills-amd-sse5-t538.html for more details. So you are just seeing the lack of AVX support. >> Details on the work to add AVX support to valgrind can be found in the bug >> tracker: https://bugs.kde.org/show_bug.cgi?id=273475 > Hm doesn't seem to get much attention since early october last year. :/ Actually Julian merged some of the preliminary work to restructure the instruction decoder back to trunk the other day. Tom -- Tom Hughes (t...@compton.nu) http://compton.nu/ ------------------------------------------------------------------------------ Keep Your Developer Skills Current with LearnDevNow! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-d2d _______________________________________________ Valgrind-users mailing list Valgrind-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/valgrind-users
