On Tue, 9 Jun 2026 06:51:43 GMT, Fei Yang <[email protected]> wrote: > Hi, please consider. > > This provides the necessary JVM changes (interpreter, c1 and c2) for a > specification-compliant Valhalla port on linux-riscv64 platform. Major change > is made in the riscv CPU part. We need a very small change to hotspot c1 > shared code. The reason is that there doesn't exist a real flag register for > the riscv64 ISA. So we have to pass the result in a temp register. That's a > major difference from other ISAs like aarch64 & amd64. > > Calling convention flattening feature has not been implemented for this > platform. If either `-InlineTypePassFieldsAsArgs` or > `-XX:-InlineTypeReturnedAsFields` is specified on the command line, JVM will > issue a warning and continue with these two options disabled. This helps > enable most of Valhalla tests on this platform so that we could have a better > test coverage. > > > > Testing on linux-riscv64: > - [x] GHA > - [x] `make test TEST="hotspot_valhalla jdk_valhalla valhalla_adopted"` > (release & fastdebug) > - [x] `make test TEST="tier1 tier2 tier3 tier4"` (release) > - [x] `make test TEST="hotspot:tier1 hotspot:tier2 hotspot:tier3 > hotspot:tier4"` (fastdebug) > > --------- > - [x] I confirm that I make this contribution in accordance with the [OpenJDK > Interim AI Policy](https://openjdk.org/legal/ai).
This pull request has now been integrated. Changeset: 1badaaa0 Author: Fei Yang <[email protected]> Committer: David Simms <[email protected]> URL: https://git.openjdk.org/valhalla/commit/1badaaa05fe852990fe85a225ef7c060d017b1c0 Stats: 2445 lines in 61 files changed: 1784 ins; 292 del; 369 mod 8386240: [lworld] Port JEP 401 to RISC-V Co-authored-by: Feilong Jiang <[email protected]> Reviewed-by: dsimms ------------- PR: https://git.openjdk.org/valhalla/pull/2531
