Each VCPU has a root page table pointer that points to the same EPT root
page. src\vbox\vmm\PGMShw.h, Enter shows how
it's set up. The same applies to AMD-V nested paging and real +
protected mode without paging.
Tom Birch wrote:
So this means the value of EPTP on each vcpu is the same?
My question before was: how do they actually share the same page
table? Is the EPT pointer copied between VCPUs (either directly or
indirectly)? Can you point to the code that does this?
cheers,
Tom
On Thu, Oct 29, 2009 at 1:58 PM, Sander van Leeuwen
<sander.vanleeu...@sun.com> wrote:
Each VCPU has its own root page table, but all VCPUs are sharing the same
one with EPT (or AMD nested paging for that matter).
Tom Birch wrote:
Cool, thanks, that's what I thought. Is there any reason the EPT is a
per-VCPU data structure? Could you please point me to the bits of code
that do this sharing? I'm getting lost looking at all the assignments
to the pShwPageCR3* variables, they still all seem to be per-VCPU, I
can't find where it hooks into the root VM structure.
cheers,
Tom
On Thu, Oct 29, 2009 at 1:19 PM, Sander van Leeuwen
<sander.vanleeu...@sun.com> wrote:
The EPT structures are shared between all VCPUs as they contain a guest
physical to host physical mapping, which
is independent of the VCPU. The host OS is irrelevant.
Tom Birch wrote:
I'm looking through the page management code, specifically hardware
acceleration on Intel with EPT, and I can't quite figure out the
high-level relationships between various structures. Both the VMCS and
EPTP seem to be per-PVMCPU data structures, does this mean that within
a single VM, you can have multiple distinct EPTPs (on different
VCpus), or is this arrangement just a consequence of the way shadow
paging worked before EPT? Put another way, can I guarantee that all
VCpus within a single VM will all share the same EPTP? I'm mainly
concerned about how this applies to Darwin if that matters, but I
seems like a fairly Host-OS-agnostic feature.
cheers,
Tom
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Kind regards / Mit freundlichen Gruessen / Met vriendelijke groet
--
Sun Microsystems GmbH Sander van Leeuwen
Werkstrasse 24 Senior Staff Engineer, VirtualBox
71384 Weinstadt, Germany mailto:sander.vanleeu...@sun.com
================================================
Sitz der Gesellschaft: Sun Microsystems GmbH,
Sonnenallee 1, 85551 Kirchheim-Heimstetten
Amtsgericht Muenchen: HRB 161028
Geschaeftsfuehrer: Thomas Schroeder,
Wolfgang Engels, Dr. Roland Boehmer
Vorsitzender des Aufsichtsrates: Martin Haering
================================================
--
Kind regards / Mit freundlichen Gruessen / Met vriendelijke groet
--
Sun Microsystems GmbH Sander van Leeuwen
Werkstrasse 24 Senior Staff Engineer, VirtualBox
71384 Weinstadt, Germany mailto:sander.vanleeu...@sun.com
================================================
Sitz der Gesellschaft: Sun Microsystems GmbH,
Sonnenallee 1, 85551 Kirchheim-Heimstetten
Amtsgericht Muenchen: HRB 161028
Geschaeftsfuehrer: Thomas Schroeder,
Wolfgang Engels, Dr. Roland Boehmer
Vorsitzender des Aufsichtsrates: Martin Haering
================================================
--
Kind regards / Mit freundlichen Gruessen / Met vriendelijke groet
--
Sun Microsystems GmbH Sander van Leeuwen
Werkstrasse 24 Senior Staff Engineer, VirtualBox
71384 Weinstadt, Germany mailto:sander.vanleeu...@sun.com
================================================
Sitz der Gesellschaft: Sun Microsystems GmbH,
Sonnenallee 1, 85551 Kirchheim-Heimstetten
Amtsgericht Muenchen: HRB 161028
Geschaeftsfuehrer: Thomas Schroeder,
Wolfgang Engels, Dr. Roland Boehmer
Vorsitzender des Aufsichtsrates: Martin Haering
================================================
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