Hi, I posted this on the OSE forum some weeks ago, but I did not get any response. I hope someone on this list can give me some guidance, because this is getting critical for me. Thanks.
I have a virtual device model plugged in through PDM, in which a PCIe switch is plugged into the ICH9 host bus, and a PCIe endpoint is connected to the secondary bus of the PCIe switch (each is a different PDM instance). The endpoint is capable of accessing system memory via DMA, which I model by calling PDMDevHlpPhysRead() and PDMDevHlpPhysWrite() from a separate thread that I have. So far so good. Now I need to add support for PCIe "atomic" operations. These are a set of endpoint initiated read/modify/write operations that are carried out without interruption. It's quite easy to implement the read/modify/write part in my model, but I am concerned about the possibility of another VirtualBox thread doing another memory access in between the read/modify/write phases. Is there a way to ensure nothing else can access memory during the critical steps of the read/modify/write? I have mutual exclusion between my own two threads, but I'm worried about guest software or other device models that are not in my control. _____________________________________________ Ric Vilbig Mentor Graphics, Emulation Division 46871 Bayside Parkway, Fremont CA, 94538 Phone: 510-354-7360 Mobile: 408-529-2365 email: [email protected]<mailto:[email protected]>
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